Altera cyclone V Technical Reference page 856

cv_5v4
2016.10.28
Register
tcwaw_and_addr_2_data
on page 13-55
re_2_we on page 13-
56
acc_clks on page 13-
57
number_of_planes
page 13-57
pages_per_block
page 13-58
device_width
13-59
device_main_area_size
on page 13-59
device_spare_area_siz
e on page 13-60
two_row_addr_cycles
on page 13-61
multiplane_addr_restr
ict on page 13-62
ecc_correction
page 13-62
read_mode on page 13-
63
write_mode on page
13-66
copyback_mode
13-67
rdwr_en_lo_cnt
page 13-68
rdwr_en_hi_cnt
page 13-69
max_rd_delay
13-70
cs_setup_cnt
13-71
spare_area_skip_bytes
on page 13-71
spare_area_marker
page 13-72
NAND Flash Controller
Send Feedback
Offset Width Acces
0x110
0x120
0x130
on 0x140
on 0x150
on page 0x160
0x170
0x180
0x190
0x1A0
on 0x1B0
0x1C0
0x1D0
on page 0x1E0
on 0x1F0
on 0x200
on page 0x210
on page 0x220
0x230
on 0x240
NAND Flash Controller Module Registers (AXI Slave) Address Map
Reset Value
s
32 RW 0x1432
32 RW 0x32
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x3
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x8
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x12
32 RW 0xC
32 RW 0x0
32 RW 0x3
32 RW 0x0
32 RW 0xFFFF
13-35
Description
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