Altera cyclone V Technical Reference page 124

cv_5v4
2016.10.28
Figure 3-4: Warm Reset Timing Diagram
nRST pin (1)
h2f_pending_rst_req_n (2)
(and other wait
request handshakes)
f2h_pending_rst_ack_n
safe_mode_req
cm_rm_safe_mode_ack
l3_rst_n
miscmod_rst_n
mpu_clkoff[0]
mpu_rst_n[0]
mpu_wd_rst_n
mpu_scu_rst_n
mpu_periph_rst_n
mpu_l2_rst_n
peripheral resets
(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins.
(2) When the nRSTpin count is zero, the 256 cycle stretch count is skipped and the start of the deassertion sequence is determined by the safe mode
acknowledge signal or the user releasing the warm reset button, whichever occurs later.
The cold and warm reset sequences consist of different reset assertion sequences and the same deassertion
sequence. The following sections describe the sequences.
Note: Cold and warm reset affect only the
running in the
Related Information
Module Reset Signals
•
• Clock Manager
For more information about safe mode, refer to the Clock Manager chapter.
Cold Reset Assertion Sequence
The following list describes the assertion steps for cold reset shown in the Cold Reset timing diagram:
1. Assert module resets
2. Wait for 32 cycles. Deassert clock manager cold reset.
3. Wait for 96 cycles (so clocks can stabilize).
4. Proceed to the "Cold and Warm Reset Deassertion Sequence" section using the following link.
Reset Manager
Send Feedback
nRST Pin Count (3)
8
cpu0
releases it.
cpu0
on page 3-5
on page 2-1
Cold Reset Assertion Sequence
256 (3)
, and by default cpu1 is held in reset until the software
Software
brings out
100 200 32 32
Altera Corporation
3-13
of reset