Altera cyclone V Technical Reference page 961

cv_5v4
2016.10.28
Bits
4 Second Address Chained (CH)
3 First Descriptor (FD)
2 Last Descriptor (LD)
1 Disable Interrupt on Completion (DIC) When set to 1, this bit prevents the setting of the TI/RI bit
0 Reserved
Table 14-7: Internal DMA Controller DES1 Descriptor Field
The DES1 descriptor field contains the buffer size.
Bits
31:26 Reserved
25:13 Buffer 2 Size (BS2)
12:0 Buffer 1 Size (BS1)
Table 14-8: Internal DMA Controller DES2 Descriptor Field
The DES2 descriptor field contains the address pointer to the data buffer.
SD/MMC Controller
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Name
When set to 1, this bit indicates that the second address in
the descriptor is the next descriptor address rather than the
second buffer address. When this bit is set to 1, BS2
(DES1[25:13]) must be all zeros.
When set to 1, this bit indicates that this descriptor
contains the first buffer of the data. If the size of the first
buffer is 0, next descriptor contains the beginning of the
data.
When set to 1, this bit indicates that the buffers pointed to
by this descriptor are the last buffers of the data.
of the internal DMA controller status register (
the data that ends in the buffer pointed to by this
descriptor.
—
Name
Internal DMA Controller Descriptor Fields
Description
†
Description
—
This field indicates the second data buffer byte size.
The buffer size must be a multiple of four. When the
buffer size is not a multiple of four, the resulting
behavior is undefined. This field is not valid if DES0[4]
is set to 1.
Indicates the data buffer byte size, which must be a
multiple of four bytes. When the buffer size is not a
multiple of four, the resulting behavior is undefined. If
this field is 0, the DMA ignores the buffer and
proceeds to the next descriptor for a chain structure,
or to the next buffer for a dual-buffer structure.
If there is only one descriptor and only one buffer to
be programmed, you need to use only buffer 1 and not
buffer 2.
†
14-15
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