Altera cyclone V Technical Reference page 481

cv_5v4
2016.10.28
Offset:
0x0
Access:
WO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
remap Fields
Bit
4
lwhps2fpga
3
hps2fpga
System Interconnect
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Controls whether the Lightweight HPS2FPGA AXI
Bridge is visible to L3 masters or not.
Value
0x0
0x1
Controls whether the HPS2FPGA AXI Bridge is
visible to L3 masters or not.
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Description
The LWHPS2FPGA AXI Bridge is not visible
to L3 masters. Accesses to the associated
address range return an AXI decode error to
the master.
The LWHPS2FPGA AXI Bridge is visible to
L3 masters.
Description
The HPS2FPGA AXI Bridge is not visible to
L3 masters. Accesses to the associated address
range return an AXI decode error to the
master.
The HPS2FPGA AXI Bridge is visible to L3
masters.
remap
21 20 19 18
5 4 3 2
lwhps hps2f Reser
2fpga pga ved
WO WO
0x0 0x0
Access
WO
WO
7-33
17 16
1 0
nonmp mpuzero
uzero
WO 0x0
WO
0x0
Reset
0x0
0x0
Altera Corporation