Introduction To The Hard Processor System - Altera cyclone V Technical Reference

Hard processor system
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2016.10.28
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The Cyclone
V system-on-a-chip (SoC) is composed of two distinct portions- a single- or dual-core
®
ARM
Cortex
®
of peripherals that reduce board size and increase performance within a system.
The SoC features the FPGA I/O, which is I/O pins dedicated to the FPGA fabric.
Figure 1-1: Altera SoC Device Block Diagram
The HPS consists of the following types of modules:
• Microprocessor unit (MPU) subsystem with single or dual ARM Cortex-A9 MPCore
• Flash memory controllers
• SDRAM controller subsystem
• System interconnect
• On-chip memories
• Support peripherals
• Interface peripherals
• Debug components
• Phase-locked loops (PLLs)
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©
are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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Introduction to the Hard Processor System

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-A9 hard processor system (HPS) and an FPGA. The HPS architecture integrates a wide set
Altera SoC Device
HPS Portion
Flash
SDRAM Controller
Subsystem
Controllers
Cortex-A9 MPU Subsystem
On-Chip
Support
Memories
Peripherals
Interface
PLLs
Debug
Peripherals
FPGA Portion
Control
User
Block
I/O
HPS-FPGA
FPGA Fabric
Interfaces
(LUTs, RAMs, Multipliers & Routing)
Hard
PLLs
PCIe
HSSI
Transceivers
Hard Memory
Controllers
processors
®
9001:2008
Registered
1
ISO

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