Altera cyclone V Technical Reference page 989

cv_5v4
2016.10.28
• The response timeout field (
• The data timeout field (
• 10 * N
N
= 10 * ((TAAC * F
where:
TAAC = Time-dependent factor of the data access time
F
NSAC = Worst-case clock rate-dependent factor of the data access time
• Host FIFO buffer latency
On read: Time elapsed before host starts reading from a full FIFO buffer
On write: Time elapsed before host starts writing to an empty FIFO buffer
• Debounce counter register (
• TX watermark field (
threshold value is set to 512, which is half the FIFO buffer depth.
• RX watermark field (
These registers do not need to be changed with every SD/MMC/CE-ATA command. Set them to a typical
value according to the SD/MMC/CE-ATA specifications.
Related Information
Clock Setup
•
Refer to this section for information on setting the clock source assignments.
Enumerated Card Stack
•
Refer to this section for information on discovering the card stack according to the card type.
Enumerated Card Stack
The card stack performs the following tasks:
• Discovers the connected card
• Sets the relative Card Address Register (RCA) in the connected card
• Reads the card specific information
• Stores the card specific information locally
The card connected to the controller can be an MMC, CE-ATA, SD or SDIO (including IO ONLY, MEM
ONLY and COMBO) card.
Identifying the Connected Card Type
To identify the connected card type, the following discovery sequence is needed:
1. Reset the card width 1 or 4 bit (
register to 0.
2. Identify the card type as SD, MMC, SDIO or SDIO-COMBO:
SD/MMC Controller
Send Feedback
response_timeout
data_timeout
†
AC
= card device total access time
AC
) + (100 * NSAC))
OP
†
= The card clock frequency used for the card operation
OP
†
debnce
tx_wmark
rx_wmark
on page 14-46
on page 14-43
†
card_width2
) of the
tmout
) of the register, highest of the following:
tmout
†
†
). A typical debounce value is 25 ms.
) of the FIFO threshold watermark register (
) of the egister. Typically, the threshold value is set to 511.
fifoth r
†
†
) and card width 8 bit (
Enumerated Card Stack
register. A typical value is
†
†
†
†
†
†
). Typically, the
fifoth
†
†
) fields in the
card_width1
14-43
†
.
0x40
†
†
ctype
Altera Corporation