Altera cyclone V Technical Reference page 173

4-30
gpio_inttype_level
Bit
3
crc
2
id
1
cd
0
ns
gpio_inttype_level
The interrupt level register defines the type of interrupt (edge or level) for each GPIO input.
Module Instance
fpgamgrregs
Altera Corporation
Name
Controls whether an interrupt for CRC_ERROR can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for INIT_DONE can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for CONF_DONE can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
Controls whether an interrupt for nSTATUS can
generate an interrupt to the interrupt controller by
not masking it. The unmasked status can be read as
well as the resultant status after masking.
Value
0x0
0x1
0xFF706000
Description
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
Description
Unmask Interrupt
Mask Interrupt
Base Address
0xFF706838
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
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cv_5v4