Altera cyclone V Technical Reference page 703

cv_5v4
2016.10.28
EPFALLOC
EPFHIT
EPFRCVDS0
EPFRCVDS1
IPFALLOC
IRHIT
IRREQ
SPNIDEN
SRCONFS0
SRCONFS1
SRRCVDS0
SRRCVDS1
WA
In addition, the L2 cache events can be captured and timestamped using dedicated debugging circuitry.
Related Information
ARM Infocenter
For more information about L2 event capture, refer to the Debug chapter of the Cortex-A9 MPCore
Technical Reference Manual, available on the ARM Infocenter website.
L2 Cache Address Filtering
The L2 cache can access either the system interconnect fabric or the SDRAM. The L2 cache address
filtering determines how much address space is allocated to the HPS-to-FPGA bridge and how much is
allocated to SDRAM, depending on the configuration of the memory management unit.
Related Information
Cortex-A9 MPU Subsystem with System Interconnect
•
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Event
L2 Cache Address Filtering
Description
Prefetch hint allocated into the L2 cache.
Prefetch hint hits in the L2 cache.
Prefetch hint received by slave port S0.
Prefetch hint received by slave port S1.
Allocation of a prefetch generated by L2 cache
controller into the L2 cache.
Instruction read hit in the L2 cache.
Instruction read lookup to the L2 cache.
Subsequently results in a hit or miss.
Secure privileged non-invasive debug enable.
Speculative read confirmed in slave port S0.
Speculative read confirmed in slave port S1.
Speculative read received by slave port S0.
Speculative read received by slave port S1.
Allocation into the L2 cache caused by a write (with
write-allocate attribute) miss.
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