Document Revision History - Altera cyclone V Technical Reference

13-124

Document Revision History

31 30
15 14
lun_status_cmd Fields
Bit
15:0
value
Document Revision History
Table 13-19: Document Revision History
Date
October 2016
May 2016
May 2016
November 2015
May 2015
December 2014
July 2014
Altera Corporation
29 28 27 26
13 12 11 10
Name
[list][*]7:0 - Indicates the command to check the
status of the first LUN/Die. [*]15:8 - Indicates the
command to check the status of the other LUN/Die.[/
list]
Version
2016.10.28 Added content about the local memory buffer
2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V
SoC webpage.
2016.05.03 Maintenance release
2015.11.02
• Moved "Interface Signals" section after "NAND Flash Controller
Block Diagram and System Integration" section and renamed it to
"NAND Flash Controller Signal Description"
• Updated the Interrupt and DMA Enabling section to recommend
reading back a register to ensure clearing an interrupt status
• Specified the valid values for Burst Length in the Command-Data
Pair 4 table
• Updated the description of
bit for intr_status0/1/2/3 and intr_en0/1/2/3
2015.05.04 Added information about clearing out the ECC before the feature is
enabled
2014.12.15 Maintenance release
2014.07.31 Updated address map and register definitions.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x7878
Description
dma_cmd_comp
21 20 19 18
5 4 3 2
Access
Changes
and added a RESERVED
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x7878
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