Altera cyclone V Technical Reference page 513

Hard processor system
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cv_5v4
2016.10.28
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
comp_id_1 Fields
Bit
7:0
genipcompcls_preamble
comp_id_2
Component ID2
Module Instance
l3regs
Offset:
0x1FF8
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
System Interconnect
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
Generic IP component class, Preamble
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
comp_id_2
21
20
19
18
5
4
3
2
genipcompcls_preamble
RO 0xF0
Access
Register Address
0xFF801FF8
21
20
19
18
5
4
3
2
preamble
RO 0x5
7-65
17
16
1
0
Reset
RO
0xF0
17
16
1
0
Altera Corporation

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