Altera cyclone V Technical Reference page 338

5-144
MIXED1IO12
MIXED1IO11 Fields
Bit
1:0
sel
MIXED1IO12
This register is used to control the peripherals connected to nand_dq7 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x530
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED1IO12 Fields
Bit
1:0
sel
Altera Corporation
Name
Select peripheral signals connected nand_dq6. 0 : Pin
is connected to GPIO/LoanIO number 25. 1 : Pin is
connected to Peripheral signal USB1.D7. 2 : Pin is
connected to Peripheral signal RGMII1.RXD1. 3 : Pin
is connected to Peripheral signal NAND.dq6.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected nand_dq7. 0 : Pin
is connected to GPIO/LoanIO number 26. 1 : Pin is
connected to Peripheral signal not applicable. 2 : Pin
is connected to Peripheral signal RGMII1.RXD2. 3 :
Pin is connected to Peripheral signal NAND.dq7.
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Access
Register Address
0xFFD08530
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
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