Altera cyclone V Technical Reference page 349

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED2IO4 Fields
Bit
1:0
sel
MIXED2IO5
This register is used to control the peripherals connected to emac1_rx_ctl Only reset by a cold reset
(ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no
support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x56C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected emac1_rx_clk. 0 :
Pin is connected to GPIO/LoanIO number 58. 1 : Pin
is connected to Peripheral signal SPIM1.CLK. 2 : Pin
is connected to Peripheral signal SPIS1.CLK. 3 : Pin is
connected to Peripheral signal RGMII1.RX_CLK.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
MIXED2IO5
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD0856C
21 20 19 18
5 4 3 2
5-155
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
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