Security Usage - Altera cyclone V Technical Reference

16-26

Security Usage

After an abort occurs, the action of the DMAC depends on the thread type:
• DMA channel thread—The thread immediately moves to the Faulting completing state. In this state,
the DMAC performs the following operations:
• Sets the
• Stops executing instructions for the DMA channel.
• Invalidates all cache entries for the DMA channel updates the
the aborted instruction provided that the abort is precise.
• Does not generate AXI accesses for any instructions remaining in the read queue and write queue.
• Permits currently active AXI transactions to complete.
Note: After the transactions for the DMA channel finish, the thread moves to the Faulting state.
• DMA manager thread—The thread immediately moves to the Faulting state and the DMAC sets the
irq_abort
The external agent can respond to the assertion of the
• Reading the status of the
state, the
• Reading the status of the
state, the
To enable a thread in the Faulting state to move to the Stopped state, the external agent must:
• Program the
• Write to the
Note: If the aborted thread is secure, you must use the secure slave interface to update these registers.
After a thread in the Faulting state executes
Security Usage
When the DMAC exits from reset, the status of the configuration signals configures the security for:
• DMA manager thread—The
thread.
• Events and interrupts—The
resources.
• Peripheral request interfaces—The
interfaces.
Additionally, each DMA channel thread contains a dynamic non-secure bit,
channel is not in the Stopped state.
Altera Corporation
signal high.
irq_abort
signal high.
register to determine if the DMA manager is Faulting. In the Faulting
FSRD
register provides the cause of the abort.
FSRD
register to determine if a DMA channel is Faulting. In the Faulting
FSRC
register provides the cause of the abort.
FSRC
register with the encoding for the
DBGINST0
register.
DBGCMD
bit in the DSR register returns the security state of the DMA manager
DNS
bit in the
INS
PNS
irq_abort
DMAKILL
, it moves to the Stopped state.
DMAKILL
register returns the security state of the event-interrupt
CR3
bit in the register returns the security state of these
CR4
register to contain the address of
CPCn
signal by all of the following:
instruction.
, that is valid when the
CNS
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2016.10.28
DMA Controller