Altera cyclone V Technical Reference page 248

5-54
Boot ROM Code Register Group Register Descriptions
Offset:
0x80
Access:
RW
31 30
15 14
handoff Fields
Bit
31:0
value
Boot ROM Code Register Group Register Descriptions
Registers used by the Boot ROM code. All fields are only reset by a cold reset (ignore warm reset).
Offset:
0xc0
ctrl
on page 5-54
Contains information used to control Boot ROM code.
cpu1startaddr
When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset exception address (the
typical case), the Boot ROM reset handler code reads the address stored in this register and jumps it to
hand off execution to user software.
initswstate
The preloader software (loaded by the Boot ROM) writes the magic value 0x49535756 (ISWV in ASCII) to
this register when it has reached a valid state.
initswlastld
Contains the index of the last preloader software image loaded by the Boot ROM from the boot device.
bootromswstate
32-bits general purpose register used by the Boot ROM code. Actual usage is defined in the Boot ROM
source code.
Warm Boot from On-Chip RAM Group Register Descriptions
Registers used by the Boot ROM code to support booting from the On-chip RAM on a warm reset. All
these registers must be written by user software before a warm reset occurs to make use of this feature.
ctrl
Contains information used to control Boot ROM code.
Altera Corporation
to
0x9C
29 28 27 26
13 12 11 10
Name
Preloader Handoff Information.
on page 5-56
on page 5-57
on page 5-57
on page 5-58
Bit Fields
25 24 23 22
value
RW 0x0
9 8 7 6
value
RW 0x0
Description
21 20 19 18
5 4 3 2
Access
on page 5-58
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
System Manager
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