Altera cyclone V Technical Reference page 46

cv_5v4
2016.10.28
Figure 2-3: Main Clock Group Divide and Gating
mpu_base_clk
Main
C0
PLL 0
main_base_clk
C1
dbg_base_clk
C2
main_qspi_base_clk
C3
main_nand_sdmmc_base_clk
C4
cfg_h2f_user0_base_clk
C5
periph_base_clk (from Peripheral PLL C4)
The clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that
a clean transition occurs, and can have the following control values changed dynamically by software write
accesses to the control registers:
• PLL bypass
• PLL numerator, denominator, and counters
• External dividers
For these registers, hardware detects that the write has occurred and performs the correct sequence to
ensure that a glitch-free transition to the new clock value occurs. These clocks can pause during the
transition.
Table 2-6: Main Clock Group Clocks
System Clock Name
mpu_clk
mpu_l2_ram_clk
Clock Manager
Send Feedback
Clock Gate
Clock Gate
Clock Gate
To Flash
Controller
Clocks
1, 2, 4, 8, or 16
Frequency
Main PLL C0
/2
mpu_clk
Main Clock Group
Divide
by 4
Divide
by 2
Divide
by 1 or 2
Divide
by 1 or 2
Divide by
1, 2, 4, 8, or 16
Divide by
1, 2, 4, 8, or 16
Divide by
1, 2, or 4
Divide
by 2 or 4
Divide by
Constraints and Notes
Clock for MPU subsystem,
including CPU0 and CPU1
Clock for MPU level 2 (L2) RAM
2-9
mpu_periph_clk
mpu_l2_ram_clk
mpu_clk
Clock Gate l4_main_clk
l3_main_clk
l3_mp_clk
Clock Gate
l3_sp_clk
l4_mp_clk
Clock Gate
l4_sp_clk
Clock Gate
dbg_at_clk
Clock Gate
dbg_clk
Clock Gate
dbg_trace_clk
Clock Gate
dbg_timer_clk
Clock Gate
cfg_clk
Clock Gate
h2f_user0_clock
Clock Gate
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