Altera cyclone V Technical Reference page 665

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2016.10.28
For a cache miss during a write access, the invalidation is considered as complete and the ACP request is
sent to L2 memory.
For a cache miss during a read access, the request is forwarded to L2 memory, which returns the data
directly to the ACP.
Note: Shared write requests are always transferred to the L2 memory once the cache line is potentially
clean and invalidated in the L1 cache memory. Reads are observed on the L2 only if they miss in the
L1 cache.
AXI Master Configuration for ACP Access
To use the ACP for coherent accesses, the following configurations apply:
ACP master configurations must be as follows:
• The master module must target the ACP in physical memory (address 0x80000000 to 0xC0000000)
• For coherent ACP read accesses, the AXI bits must be programmed as follows to avoid compromising
coherency:
•
AxCACHE[3:0]
tables for the relevant memory region.
• Shareable attribute
The Cortex-A9 MPCore configuration for ACP use should be as follows:
• The Snoop Control Unit must be enabled (by setting the SCU enable bit in the SCU Control Register at
0xFFFEC000).
• Coherent memory must be marked cacheable and shareable.
• The
SMP
Note: It is recommended that the
Control
change the point of coherency and cause errors. If this bit is clear, non-cacheable accesses from the
MPU cores or ACP port may be transformed into cacheable non-allocated accesses and the point of
coherency moves from the SDRAM to the L2 cache.
Note: To achieve maximum performance on the ACP, avoid switching from shared to non-shared
requests and vice-versa. When a shared request is latched in the ACP and there are non-shared
requests still pending, the non-shared requests must be completed before the shared request can
proceed.
The following sections detail the attribute configurations necessary to support coherency.
Related Information
CoreLink Level 2 Cache Controller L2C-310, Revision: r3p3 Technical Reference Manuel
For more information about shareable attributes
Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses
The following list highlights how to correctly derive and apply the correct
accesses.
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
attributes must match the properties defined in the Cortex-A9 MPCore MMU page
AxUSER[0]
bit of the register must be set in the Cortex-A9 processor that shares data over the ACP.
ACTLR
shared attribute override enable bit [22]
register is set. Enabling this bit disables optimizations in the L2 cache controller that can
AXI Master Configuration for ACP Access
must be set to 0x1
in the
Auxiliary
settings for coherent
AxCACHE
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