Altera cyclone V Technical Reference page 634

8-52
HPS-to-FPGA Bridge Clocks and Resets
logic. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock
domain, asynchronous from the HPS.
The FPGA-to-HPS bridge has one reset signal,
signal to the FPGA-to-HPS bridge on a cold or warm reset.
Related Information
Clock Manager
•
HPS Component Interfaces
•
Information about the HPS-FPGA bridge clock interfaces
HPS-to-FPGA Bridge Clocks and Resets
The master interface into the FPGA fabric operates in the
clock is provided by user logic. The slave interface of the bridge in the HPS logic operates in the
l3_main_clk
operate in any clock domain, asynchronous from the HPS.
The HPS-to-FPGA bridge has one reset signal,
signal to the HPS-to-FPGA bridge on a cold or warm reset.
Related Information
Clock Manager
•
HPS Component Interfaces
•
Information about the HPS-FPGA bridge clock interfaces
Lightweight HPS-to-FPGA Bridge Clocks and Resets
The master interface into the FPGA fabric operates in the
provided by custom logic in the FPGA fabric. The slave interface of the bridge in the HPS logic operates in
the
l4_mp_clk
operate in any clock domain, asynchronous from the HPS.
The lightweight HPS-to-FPGA bridge has one reset signal,
drives this signal to the lightweight HPS-to-FPGA bridge on a cold or warm reset.
Related Information
Clock Manager
•
HPS Component Interfaces
•
Information about the HPS-FPGA bridge clock interfaces
Taking HPS-FPGA Bridges Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Related Information
Modules Requiring Software Deassert
Reset register names
Altera Corporation
on page 2-1
on page 28-1
clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to
on page 2-1
on page 28-1
clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to
on page 2-1
on page 28-1
fpga2hps_bridge_rst_n
h2f_axi_clk
hps2fpga_bridge_rst_n
h2f_lw_axi_clk
lwhps2fpga_bridge_rst_n
on page 3-9
. The reset manager drives this
clock domain. The
h2f_axi_clk
. The reset manager drives this
clock domain. The clock is
. The reset manager
HPS-FPGA Bridges
Send Feedback
cv_5v4
2016.10.28