Altera cyclone V Technical Reference page 84

cv_5v4
2016.10.28
l4src Fields
Bit
1
l4sp
0
l4mp
stat
Contains Output Clock Counter Reset acknowledge status.
Module Instance
clkmgr
Offset:
0x74
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Clock Manager
Send Feedback
Name
Selects the source for l4_sp_clk
Value
0x0
0x1
Selects the source for l4_mp_clk
Value
0x0
0x1
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Description
main_clk
periph_base_clk
Description
main_clk
periph_base_clk
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
RW
RW
Register Address
0xFFD04074
21 20 19 18
5 4 3 2
outresetack
RO 0x0
2-47
stat
Reset
0x0
0x0
17 16
1 0
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