Altera cyclone V Technical Reference page 656

9-20
GIC Interrupt Map for the Cyclone V SoC HPS
GIC Source Block
Interrupt
Number
131 FPGA
132 FPGA
133 FPGA
134 FPGA
135 FPGA
136 DMA
137 DMA
138 DMA
139 DMA
140 DMA
141 DMA
142 DMA
143 DMA
144 DMA
145 DMA
146 DMA
147 EMAC0
148 EMAC0
149 EMAC0
Altera Corporation
Interrupt Name
FPGA_IRQ59
FPGA_IRQ60
FPGA_IRQ61
FPGA_IRQ62
FPGA_IRQ63
dma_IRQ0
dma_IRQ1
dma_IRQ2
dma_IRQ3
dma_IRQ4
dma_IRQ5
dma_IRQ6
dma_IRQ7
dma_irq_abort
dma_ecc_corrected_IRQ
dma_ecc_uncorrected_IRQ
emac0_IRQ
emac0_tx_ecc_corrected_IRQ
emac0_tx_ecc_uncorrected_
IRQ
Combined Interrupts
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
This interrupt combines:
and
intr_o lpi_intr_o
—
—
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
Triggering
Level or
Edge
Level or
Edge
Level or
Edge
Level or
Edge
Level or
Edge
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
sbd_
.
Level
Level
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