Altera cyclone V Technical Reference page 971

cv_5v4
2016.10.28
CCS Timeout
If the command expects a CCS from the card device (the
the command state machine waits for the CCS and remains in the wait CCS state. If the CE-ATA card fails
to send out the CCS, the host software must implement a timeout mechanism to free the command and
data path. The controller does not implement a hardware timer; it is the responsibility of the host software
to maintain a software timer.
In the event of a CCS timeout, the host must issue a CCSD command by setting the
register. The controller command path state machine sends the CCSD command to the CE-ATA card
ctrl
device and exits to an idle state. After sending the CCSD command, the host must also send an SD/SDIO
STOP_TRANSMISSION command to the CE-ATA card to abort the outstanding ATA command.
Send CCSD Command
If the
send_ccsd
The host can send the CCSD command while waiting for the CCS or after a CCS timeout happens.
After sending the CCSD pattern, the controller sets the
an interrupt to the host if the Command Done interrupt is not masked.
Note: Within the CIU block, if the
CCS is sampled, the CIU block does not send a CCSD pattern on the CMD line. In this case, the
dto
Note: Due to asynchronous boundaries, the CCS might have already happened and the
set to 1. In this case, the CCSD command does not go to the CE-ATA card device and the
send_ccsd
is issued.
If the send auto stop CCSD (
sends an internally generated STOP_TRANSMISSION command (CMD12) after sending the CCSD
pattern. The controller sets the
I/O transmission delay (N
The host software maintains the timeout mechanism for handling the I/O transmission delay (N
cycles) time-outs while reading from the CE-ATA card device. The controller neither maintains any
timeout mechanism nor indicates that N
token. The I/O transmission delay is applicable for read transfers using the RW_REG and RW_BLK
commands; the RW_REG and RW_BLK commands used in this document refer to the
RW_MULTIPLE_REGISTER and RW_MULTIPLE_BLOCK MMC commands defined by the CE-ATA
specification.
Note: After the N
commands, or the STOP command. The Data Read Timeout (DRTO) interrupt might be set to 1
while a STOP_TRANSMISSION command is transmitted out of the controller, in which case the
data read timeout boot data start bit (
Data Path
The data path block reads the data FIFO buffer and transmits data on the card bus during a write data
transfer, or receives data and writes it to the FIFO buffer during a read data transfer. The data path loads
new data parameters—data expected, read/write data transfer, stream/block transfer, block size, byte
count, card type, timeout registers—whenever a data transfer command is not in progress. If the data
SD/MMC Controller
Send Feedback
†
bit in the register is set to 1, the controller sends a CCSD pattern on the CMD line.
ctrl
send_ccsd
and bits in the
cmd rintsts
bit is not set to 0. The host must reset the
†
send_auto_stop_ccsd
bit in the
acd
Timeout)
ACIO
†
timeout, the application must abort the command by sending the CCSD and STOP
ACIO
ccs_expected
bit in the
cmd
bit in the register is set to 1 on the same clock cycle as
ctrl
†
register are set to 1.
send_ccsd
) bit in the
ctrl
†
register.
rintsts
cycles are elapsed while waiting for the start bit of a data
ACIO
) and the bit in the
bds dto
CCS Timeout
bit is set to 1 in the
cmd
send_ccsd
register and also generates
rintsts
†
send_ccsd
bit to 0 before the next command
register is set to 1, the controller
register are set to 1.
rintsts
Altera Corporation
14-25
register),
bit in the
†
†
bit is
ACIO
†