Sdram Controller Subsystem Programming Model - Altera cyclone V Technical Reference

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SDRAM Controller Subsystem Programming Model

Name
ARCACHE
ARPROT
ARREADY
ARVALID
RID
32, 64, 128
RDATA
RRESP
RLAST
RVALID
RREADY
Related Information
ARM AMBA Open Specification
AMBA Open Specifications, including information about the AXI-3 interface
SDRAM Controller Subsystem Programming Model
SDRAM controller configuration occurs through software programming of the configuration registers
using the CSR interface.
HPS Memory Interface Architecture
The configuration and initialization of the memory interface by the ARM processor is a significant
difference compared to the FPGA memory interfaces, and results in several key differences in the way the
HPS memory interface is defined and configured.
Boot-up configuration of the HPS memory interface is handled by the initial software boot code, not by
the FPGA programmer, as is the case for the FPGA memory interfaces. The software is involved in
defining the configuration of I/O ports which is used by the boot-up code, as well as timing analysis of the
memory interface. Therefore, the memory interface must be configured with the correct PHY-level timing
information. Although configuration of the memory interface in Qsys is still necessary, it is limited to
PHY- and board-level settings.
HPS Memory Interface Configuration
To configure the external memory interface components of the HPS, open the HPS interface by selecting
the Arria V/Cyclone V Hard Processor System component in Qsys. Within the HPS interface, select the
EMIF tab to open the EMIF parameter editor.
Altera Corporation
Bits Direction
4 In
3 In
1 Out
1 In
4 Out
Out
or 256
2 Out
1 Out
1 Out
1 In
Channel
Read address Lock type signal which indicates if the
access is exclusive; valid values are 0x0
(normal access) and 0x1 (exclusive access)
Read address Protection-type signal used to indicate
whether a transaction is secure or non-
secure
Read address Indicates ready for a read command
Read address Indicates valid read command
Read data Read data transfer ID
Read data Read data
Read data Read response status
Read data Last transfer in a burst
Read data Indicates read data is valid
Read data Read data channel ready signal
2016.10.28
Function
SDRAM Controller Subsystem
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