Altera cyclone V Technical Reference page 236

5-42
src
src
Contains register field to choose between software state machine (vioctrl array index [1] register) or
hardware state machine in the Freeze Controller as the freeze signal source for VIO channel 1. All fields
are only reset by a cold reset (ignore warm reset).
Module Instance
sysmgr
Offset:
0x54
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
src Fields
Bit
0
vio1
hwctrl
Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) and monitor for
completeness and the current state. These fields interact with the hardware state machine in the Freeze
Controller. These fields can be accessed independent of the value of SRC1.VIO1 although they only have
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
The freeze signal source for VIO channel 1 (VIO bank
2 and bank 3).
Value
0x0
0x1
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
VIO1 freeze signals are driven by software
writing to the VIOCTRL[1] register. The
VIO1-related fields in the hwctrl register are
active but don't effect the VIO1 freeze signals.
VIO1 freeze signals are driven by the
hardware state machine in the Freeze
Controller. The VIO1-related fields in the
hwctrl register are active and effect the VIO1
freeze signals.
Register Address
0xFFD08054
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
17 16
1 0
vio1
RW 0x0
Reset
RW 0x0
System Manager
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