Altera cyclone V Technical Reference page 26

1-10
Reset Manager
Reset Manager
The reset manager manages both hardware and software reset sources in the HPS. Reset status is also
provided. Reset types include cold, warm, and debug. Reset behavior depends on the type.
Related Information
Reset Manager
System Manager
The system manager controls system functions and modules that need external control signals. The system
manager offers the following features:
• ECC monitoring and control
• Low-level control of peripheral features not accessible through the control and status registers (CSRs)
• Freeze controller that places I/O elements into a safe state for configuration
Related Information
System Manager
Scan Manager
The scan manager is used to configure and manage HPS I/O pins and to communicate with the FPGA
JTAG.
Related Information
Scan Manager
Timers
The four timers are based on the Synopsys DesignWare Advanced Peripheral Bus (APB) Timer peripheral
and offer the following features:
• 32-bit timer resolution
• Free-running timer mode
• Supports a time-out period of up to 43 seconds when the timer clock frequency is 100 MHz
• Interrupt generation
Related Information
Timer
on page 23-1
Watchdog Timers
The two watchdog timers are based on the Synopsys DesignWare APB Watchdog Timer peripheral and
offer the following features:
• 32-bit timer resolution
• Interrupt request
• Reset request
• Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock
frequency)
Related Information
Watchdog Timer
Altera Corporation
on page 3-1
on page 5-1
on page 6-1
on page 24-1
Introduction to the Hard Processor System
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2016.10.28