Altera cyclone V Technical Reference page 282

5-88
sdmmc
qspi Fields
Bit
4
derr
3
serr
2
injd
1
injs
0
en
sdmmc
This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected into the write path
using bits in this register. Only reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x16C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
This bit is an interrupt status bit for QSPI RAM ECC
double bit, non-correctable error. It is set by hardware
when double bit, non-correctable error occurs in
QSPI RAM. Software needs to write 1 into this bit to
clear the interrupt status.
This bit is an interrupt status bit for QSPI RAM ECC
single, correctable error. It is set by hardware when
single, correctable error occurs in QSPI RAM.
Software needs to write 1 into this bit to clear the
interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the QSPI RAM. This only
injects one double bit error into the QSPI RAM.
Changing this bit from zero to one injects a single,
correctable error into the QSPI RAM. This only
injects one error into the QSPI RAM.
Enable ECC for QSPI RAM
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFFD0816C
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
System Manager
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cv_5v4