Acp Id Mapper - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Note: If the address and burst size of the transaction to the ACP matches either of the conditions shown
in the table "Recommended Burst Types for Optimized Bursts", the logic in the MPU assumes the
transaction has all its byte strobes set. If the byte strobes are not all set, then the write does not
actually overwrite all the bytes in the word. Instead, the cache assumes the whole cache line is valid.
If this line is dirty (and therefore gets written out to SDRAM), data corruption might occur.
In addition to optimizing performance, using a 64-bit access width will allow you to use ECC. ECC is only
supported for 64-bit accesses that are 64-bit aligned..
Related Information
Single Event Upset Protection
Exclusive and Locked Accesses
The ACP does not support exclusive accesses to coherent memory. Exclusive accesses to non-coherent
memory can be generated, however, it is important that the exclusive access transaction is not affected by
the upsizing and downsizing logic of the FPGA-to-HPS bridge or the system interconnect. If the exclusive
access is broken into multiple transactions due to the sizing logic, the exclusive access bit is cleared by the
bridge or interconnect and the exclusive access fails.
Note: Altera recommends that exclusive accesses bypass the ACP altogether, either through the 32-bit
slave port of the SDRAM controller connected directly to the system interconnect or through the
FPGA-to-SDRAM interface.
The ACP ID mapper does not support locked accesses. To ensure mutually exclusive access to shared data,
use the exclusive access support built into the SDRAM controller.
Related Information
SDRAM Controller Subsystem
For more information about the exclusive access support of the SDRAM controller subsystem, refer to the
SDRAM Controller Subsystem chapter.

ACP ID Mapper

The ACP ID mapper is situated between the level 3 (L3) interconnect and the MPU subsystem ACP slave.
It is responsible for mapping 12-bit Advanced Microcontroller Bus Architecture (AMBA
eXtensible Interface (AXI
supported by the ACP slave port.
The ACP ID mapper also implements a 1 GB coherent window into the 4 GB ARM Cortex-A9 MPCore
address space.
Functional Description
The ACP slave supports up to six masters. However, custom peripherals implemented in the FPGA fabric
can have a larger number of masters that need to access the ACP slave. The ACP ID mapper allows these
masters to access the ACP.
Cortex-A9 Microprocessor Unit Subsystem
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) IDs (input IDs) from the system interconnect to 3-bit AXI IDs (output IDs)
™
Exclusive and Locked Accesses
) Advanced
®
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