Altera cyclone V Technical Reference page 964

14-18
Internal DMA Controller Functional State Machine
Internal DMA Controller Functional State Machine
The following list explains each state of the functional state machine:
1. The internal DMA controller performs four accesses to fetch a descriptor.
2. The DMA controller stores the descriptor information internally. If it is the first descriptor, the
controller issues a FIFO buffer reset and waits until the reset is complete.
3. The internal DMA controller checks each bit of the descriptor for the correctness. If bit mismatches are
found, the appropriate error bit is set to 1 and the descriptor is closed by setting the OWN bit in the
DES0 field to 1.
The
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register indicates one of the following conditions:
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SD/MMC Controller
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2016.10.28