Altera cyclone V Technical Reference page 864

cv_5v4
2016.10.28
31 30
15 14
transfer_spare_reg Fields
Bit
0
flag
load_wait_cnt
Wait count value for Load operation
Module Instance
nandregs
Offset:
0x20
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
Send Feedback
29 28 27 26
13 12 11 10
Name
On all read or write commands through Map 01, if
this bit is set, data in spare area of memory will be
transfered to host along with main area of data. The
main area will be transfered followed by spare area.
[list][*]1 - MAIN+SPARE [*]0 - MAIN[/list]
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x1F4
load_wait_cnt
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80020
21 20 19 18
5 4 3 2
13-43
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
17 16
1 0
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