Endian Support; Introduction To The Hard Processor System Address Map; Hps Address Spaces - Altera cyclone V Technical Reference

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2016.10.28
• Real-time program flow instruction trace through a separate PTM for each processor
• Host debugger JTAG interface
• Connections for cross-trigger and STM-to-FPGA interfaces, which enable soft IP cores to generate of
triggers and system trace messages
• Custom message injection through STM into trace stream for delivery to host debugger
• Capability to route trace data to any slave accessible to the ETR master, which is connected to the level
3 (L3) interconnect
Related Information
CoreSight Debug and Trace

Endian Support

The HPS is natively a little–endian system. All HPS slaves are little endian.
The processor masters are software configurable to interpret data as little endian, big endian, or byte–
invariant (BE8). All other masters, including the USB 2.0 interface, are little endian. Registers in the MPU
and L2 cache are little endian regardless of the endian mode of the CPUs.
Note: Altera strongly recommends that you only use little endian.
The FPGA–to–HPS, HPS–to–FPGA, FPGA–to–SDRAM, and lightweight HPS–to–FPGA interfaces are
little endian.
If a processor is set to BE8 mode, software must convert endianness for accesses to peripherals and DMA
linked lists in memory. The processor provides instructions to swap byte lanes for various sizes of data.
The ARM Cortex–A9 MPU supports a single instruction to change the endianness of the processor and
provides the REV and REV16 instructions to swap the endianness of bytes or half–words respectively. The
MMU page tables are software configurable to be organized as little–endian or BE8.
The ARM DMA controller is software configurable to perform byte lane swapping during a transfer.

Introduction to the Hard Processor System Address Map

The address map specifies the addresses of slaves, such as memory and peripherals, as viewed by the MPU
and other masters. The HPS has multiple address spaces, defined in the following section.
Related Information
System Interconnect

HPS Address Spaces

The following table shows the HPS address spaces and their sizes.
Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space
has the peripheral, FPGA slaves, SDRAM window, and boot regions.
The following figure shows the relationships between the HPS address spaces. The figure is not to scale.
Introduction to the Hard Processor System
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Endian Support
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