Altera cyclone V Technical Reference page 225

cv_5v4
2016.10.28
Bit
2
dctag_0
1
dcdata_1
0
dcdata_0
FPGA Interface Group Register Descriptions
Registers used to enable/disable interfaces between the FPGA and HPS. Required for either of the
following situations:[list][*]Interfaces that cannot be disabled by putting an HPS module associated with
the interface into reset.[*]HPS modules that accept signals from the FPGA fabric and those signals might
interfere with the normal operation of the module.[/list]. All registers are only reset by a cold reset (ignore
warm reset).
Offset:
0x20
gbl on page 5-31
Used to disable all interfaces between the FPGA and HPS.
indiv
on page 5-32
Used to disable individual interfaces between the FPGA and HPS.
module on page 5-35
Used to disable signals from the FPGA fabric to individual HPS modules.
gbl
Used to disable all interfaces between the FPGA and HPS.
Module Instance
sysmgr
Offset:
0x20
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Manager
Send Feedback
Name
If 1, injecting parity error to Data Cache Tag
RAM.The field array index corresponds to the CPU
index.
If 1, injecting parity error to Data Cache Data
RAM.The field array index corresponds to the CPU
index.
If 1, injecting parity error to Data Cache Data
RAM.The field array index corresponds to the CPU
index.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
FPGA Interface Group Register Descriptions
Description
Base Address
0xFFD08020
5-31
Access Reset
RW 0x0
RW 0x0
RW 0x0
Register Address
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