On-Chip Memory - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
SDRAM Controller Subsystem
SDRAM Controller
The SDRAM controller contains a multiport front end (MPFE) that accepts requests from HPS masters
and from soft logic in the FPGA fabric through the FPGA-to-HPS SDRAM interface.
The SDRAM controller offers the following features:
• Up to 4 GB address range
• 8-, 16-, and 32-bit data widths
• Optional ECC support
• Low-voltage 1.35V DDR3L and 1.2V DDR3U support
• Full memory device power management support
• Two chip selects (DDR2 and DDR3)
The SDRAM controller provides the following features to maximize memory performance:
• Command reordering (look-ahead bank management)
• Data reordering (out of order transactions)
• Deficit round-robin arbitration with aging for bandwidth management
• High-priority bypass for latency sensitive traffic
Related Information
SDRAM Controller Subsystem
DDR PHY
The DDR PHY interfaces the single port memory controller to the HPS memory I/O.
Related Information
SDRAM Controller Subsystem

On-Chip Memory

On-Chip RAM
The on-chip RAM offers the following features:
• 64 KB size
• 64-bit slave interface
• High performance for all burst lengths
Related Information
On-Chip Memory
Boot ROM
The boot ROM offers the following features:
• 64 KB size
• Contains the code required to support HPS boot from cold or warm reset
• Used exclusively for booting the HPS
Introduction to the Hard Processor System
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SDRAM Controller
Altera Corporation