Altera cyclone V Technical Reference page 130

cv_5v4
2016.10.28
Bit
24
sdrselfreftimeout
19
cdbgreqrst
18
fpgadbgrst
15
l4wd1rst
14
l4wd0rst
13
mpuwd1rst
12
mpuwd0rst
10
swwarmrst
9
fpgawarmrst
8
nrstpinrst
4
swcoldrst
3
configiocoldrst
2
fpgacoldrst
1
nporpinrst
0
porvoltrst
ctrl
The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the
cold and warm reset, enable hardware handshake with other modules before warm reset, and perform
Reset Manager
Send Feedback
Name
A 1 indicates that Reset Manager's request to the
SDRAM Controller Subsystem to put the SDRAM
devices into self-refresh mode before starting a
hardware sequenced warm reset timed-out and the
Reset Manager had to proceed with the warm reset
anyway.
DAP triggered debug reset
FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)
L4 Watchdog 1 triggered a hardware sequenced warm
reset
L4 Watchdog 0 triggered a hardware sequenced warm
reset
MPU Watchdog 1 triggered a hardware sequenced
warm reset
MPU Watchdog 0 triggered a hardware sequenced
warm reset
Software wrote CTRL.SWWARMRSTREQ to 1 and
triggered a hardware sequenced warm reset
FPGA core triggered a hardware sequenced warm
reset (f2h_warm_rst_req_n = 1)
nRST pin triggered a hardware sequenced warm reset
Software wrote CTRL.SWCOLDRSTREQ to 1 and
triggered a cold reset
FPGA entered CONFIG_IO mode and a triggered a
cold reset
FPGA core triggered a cold reset (f2h_cold_rst_req_n
= 1)
nPOR pin triggered a cold reset (por_pin_req = 1)
Built-in POR voltage detector triggered a cold reset
(por_voltage_req = 1)
Description
3-19
ctrl
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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