Altera cyclone V Technical Reference page 477

cv_5v4
2016.10.28
On-chip RAM
Register
fn_mod_bm_iss
7-96
wr_tidemark on page
7-97
fn_mod on page 7-98
DAP
Register
fn_mod2 on page 7-99
fn_mod_ahb on page 7-
100
read_qos on page 7-
101
write_qos on page 7-
102
fn_mod on page 7-103
MPU
Register
read_qos on page 7-
104
write_qos on page 7-
104
fn_mod on page 7-105
System Interconnect
Send Feedback
Offset Width Acces
on page 0x27008
0x27040
0x27108
Offset Width Acces
0x42024
0x42028
0x42100
0x42104
0x42108
Offset Width Acces
0x43100
0x43104
0x43108
L3 (NIC-301) GPV Registers Address Map
Reset Value
s
32 RW 0x0
32 RW 0x4
32 RW 0x0
Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
Description
Bus Matrix Issuing Functionality
Modification Register
Write Tidemark
Issuing Functionality Modification
Register
Description
Functionality Modification 2
Register
Functionality Modification AHB
Register
Read Channel QoS Value
Write Channel QoS Value
Issuing Functionality Modification
Register
Description
Read Channel QoS Value
Write Channel QoS Value
Issuing Functionality Modification
Register
Altera Corporation
7-29