cv_5v4
2016.10.28
The system manager consists of the following:
• CSRs—Provide memory-mapped access to control signals and status for the following HPS modules:
• EMACs
• Debug core
• SD/MMC controller
• NAND controller
• USB controllers
• DMA controller
• System interconnect
• ECC memory interfaces for the following peripherals:
• USB controllers
• SD/MMC controller
• Ethernet MACs
• DMA controller
• NAND flash controller
• On-chip RAM
• Slave port interface—provides access to system manager CSRs for connected masters.
• Watchdog debug pause—accepts the debug mode status from the MPU subsystem and pauses the L4
watchdog timers.
• Reset Manager— system manager receives the reset signals from reset manager.
Functional Description of the System Manager
The system manager serves the following purposes:
• Provides software access to boot configuration and system information
• Provides software access to control and status signals in other HPS modules
• Provides combined ECC status and interrupt from other HPS modules with ECC-protected RAM
• Enables and disables HPS peripheral interfaces to the FPGA
• Provides eight registers that software can use to pass information between boot stages
Boot Configuration and System Information
The system manager provides boot configuration information through the
value of the HPS boot select (
The boot source is determined by a combination of the
pins.
Related Information
Booting and Configuration
Additional Module Control
Each module in the HPS has its own CSRs, providing access to the internal state of the module. The system
manager provides registers for additional module control and monitoring. To fully control each module,
System Manager
Send Feedback
Functional Description of the System Manager
) pins are available to the Boot ROM software.
BSEL
on page 30-1
bootinfo
pins and a fuse bit that can bypass the
BSEL
5-3
register. Sampled
BSEL
Altera Corporation