Altera cyclone V Technical Reference page 5

Document Revision History.....................................................................................................................8-54
Cortex-A9 Microprocessor Unit Subsystem....................................................... 9-1
Features of the Cortex-A9 MPU Subsystem.............................................................................................9-1
Cortex-A9 MPU Subsystem Block Diagram and System Integration.................................................. 9-2
Cortex-A9 MPU Subsystem with System Interconnect..............................................................9-2
Cortex-A9 MPU Subsystem Internals...........................................................................................9-3
Cortex-A9 MPCore......................................................................................................................................9-4
Functional Description....................................................................................................................9-4
Implementation Details...................................................................................................................9-5
Cortex-A9 Processor........................................................................................................................9-6
Interactive Debugging Features......................................................................................................9-7
L1 Caches.......................................................................................................................................... 9-7
Preload Engine..................................................................................................................................9-7
Floating Point Unit...........................................................................................................................9-8
NEON Multimedia Processing Engine......................................................................................... 9-8
Memory Management Unit............................................................................................................ 9-9
Performance Monitoring Unit......................................................................................................9-12
ARM Cortex-A9 MPCore Timers............................................................................................... 9-12
Generic Interrupt Controller........................................................................................................9-13
Global Timer...................................................................................................................................9-25
Snoop Control Unit....................................................................................................................... 9-26
Accelerator Coherency Port..........................................................................................................9-27
ACP ID Mapper......................................................................................................................................... 9-31
Functional Description..................................................................................................................9-31
Implementation Details.................................................................................................................9-32
ACP ID Mapper Address Map and Register Definitions..........................................................9-37
L2 Cache......................................................................................................................................................9-61
Functional Description..................................................................................................................9-61
CPU Prefetch.............................................................................................................................................. 9-68
Debugging Modules...................................................................................................................................9-68
Program Trace................................................................................................................................ 9-68
Event Trace......................................................................................................................................9-69
Cross-Triggering............................................................................................................................ 9-69
Clocks.......................................................................................................................................................... 9-70
Cortex-A9 MPU Subsystem Register Implementation.........................................................................9-70
Cortex-A9 MPU Subsystem Address Map................................................................................. 9-71
L2 Cache Controller Address Map.............................................................................................. 9-72
Document Revision History.....................................................................................................................9-73
CoreSight Debug and Trace...............................................................................10-1
Features of CoreSight Debug and Trace..................................................................................................10-2
ARM CoreSight Documentation............................................................................................................. 10-2
CoreSight Debug and Trace Block Diagram and System Integration.................................................10-3
Functional Description of CoreSight Debug and Trace........................................................................10-4
Debug Access Port......................................................................................................................... 10-4
System Trace Macrocell.................................................................................................................10-4
TOC-5
Altera Corporation