Altera cyclone V Technical Reference page 558

7-110
DMA Register Descriptions
fn_mod Fields
Bit
1
wr
0
rd
DMA Register Descriptions
Registers associated with the DMA Controller slave interface. This slave is used by the DMA Controller to
access slaves attached to the L3/L4 Interconnect.
Offset:
0x3000
read_qos
on page 7-110
QoS (Quality of Service) value for the read channel.
write_qos
QoS (Quality of Service) value for the write channel.
fn_mod on page 7-112
Sets the block issuing capability to multiple or single outstanding transactions.
read_qos
QoS (Quality of Service) value for the read channel.
Module Instance
l3regs
Offset:
0x45100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-111
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
0xFF800000
Access
Register Address
0xFF845100
System Interconnect
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
Send Feedback