Altera cyclone V Technical Reference page 263

cv_5v4
2016.10.28
l3master
Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated
only during system initialization prior to removing the peripheral from reset. They may not be changed
dynamically during peripheral operation All fields are reset by a cold or warm reset.
Module Instance
sysmgr
Offset:
0x114
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
awcache_0
RW 0x0
l3master
Register Address
0xFFD08114
21 20 19 18
5 4 3 2
arcache_0
RW 0x0
5-69
17 16
1 0
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