Altera cyclone V Technical Reference page 139

3-28
per2modrst
Module Instance
rstmgr
Offset:
0x18
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
per2modrst Fields
Bit
7
dmaif7
6
dmaif6
5
dmaif5
4
dmaif4
3
dmaif3
2
dmaif2
1
dmaif1
0
dmaif0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Resets DMA channel 7 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 6 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 5 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 4 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 3 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 2 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 1 interface adapter between
FPGA Fabric and HPS DMA Controller
Resets DMA channel 0 interface adapter between
FPGA Fabric and HPS DMA Controller
Base Address
0xFFD05000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dmaif dmaif
7 6
RW RW
0x1 0x1
Description
Register Address
0xFFD05018
21 20 19 18
5 4 3 2
dmaif dmaif dmaif dmaif
5 4 3 2
RW RW RW RW
0x1 0x1 0x1 0x1
cv_5v4
2016.10.28
17 16
1 0
dmaif dmaif0
1
RW 0x1
RW
0x1
Access Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
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