Altera cyclone V Technical Reference page 158

cv_5v4
2016.10.28
ctrl
Allows HPS to control FPGA configuration. The NCONFIGPULL, NSTATUSPULL, and
CONFDONEPULL fields drive signals to the FPGA Control Block that are logically ORed into their
respective pins. These signals are always driven independent of the value of EN. The polarity of the
NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their associated
pins. The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of operation for
Normal Configuration. For Partial Reconfiguration, CDRATIO is used to set the appropriate clock to data
ratio, and CFGWDTH should always be set to 16-bit Passive Parallel. AXICFGEN is used to enable
transfer of configuration data by enabling or disabling DCLK during data transfers.
Module Instance
fpgamgrregs
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
FPGA Manager
Send Feedback
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
cfgwd axicf cdratio
th gen
RW 0x0
RW RW
0x1 0x0
Register Address
0xFF706004
21 20 19 18
5 4 3 2
prreq confd nstat nconf
onepu uspul igpul
RW
ll l l
0x0
RW RW RW
0x0 0x0 0x0
4-15
ctrl
17 16
1 0
nce en
RW RW 0x0
0x0
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