Altera cyclone V Technical Reference page 962

14-16
Host Bus Burst Access
Bits
31: Buffer Address Pointer 1 (BAP1)
0
Table 14-9: Internal DMA Controller DES3 Descriptor Field
The DES3 descriptor field contains the address pointer to the next descriptor if the present descriptor is
not the last descriptor in a chained descriptor structure or the second buffer address for a dual-buffer
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structure.
Bits
31:0 Buffer Address Pointer 2 (BAP2) or
Next Descriptor Address
Host Bus Burst Access
The internal DMA controller attempts to issue fixed-length burst transfers on the master interface if
configured using the fixed burst bit (
limited by the programmable burst length (
fetched, the master interface always presents a burst size of four to the interconnect.
The internal DMA controller initiates a data transfer only when sufficient space to accommodate the
configured burst is available in the FIFO buffer or the number of bytes to the end of transfer is less than
the configured burst-length. When the DMA master interface is configured for fixed-length bursts, it
transfers data using the most efficient combination of INCR4, INCR8 or INCR16 and SINGLE transac‐
tions. If the DMA master interface is not configured for fixed length bursts, it transfers data using INCR
(undefined length) and SINGLE transactions.
Host Data Buffer Alignment
The transmit and receive data buffers in system memory must be aligned to a 32-bit boundary.
Buffer Size Calculations
The driver knows the amount of data to transmit or receive. For transmitting to the card, the internal
DMA controller transfers the exact number of bytes from the FIFO buffer, indicated by the buffer size field
of the DES1 descriptor field.
If a descriptor is not marked as last (with the LD bit of the DES0 field set to 0) then the corresponding
buffer(s)​ of the descriptor are considered full, and the amount of valid data in a buffer is accurately
indicated by its buffer size field. If a descriptor is marked as last, the buffer might or might not be full, as
indicated by the buffer size in the DES1 field. The driver is aware of the number of locations that are valid.
The driver is expected to ignore the remaining, invalid bytes.
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) of the
fb
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These bits indicate the physical address of the first data
buffer. The internal DMA controller ignores DES2 [1:0],
because it only performs 32-bit aligned accesses.
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These bits indicate the physical address of the second buffer
when the dual-buffer structure is used. If the Second
Address Chained (DES0[4]) bit is set to 1, this address
contains the pointer to the physical memory where the
next descriptor is present.
If this is not the last descriptor, the next descriptor address
pointer must be aligned to 32 bits. Bits 1 and 0 are ignored.
register. The maximum burst length is indicated and
bmod
) field of the register. When descriptors are being
pbl bmod
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Description
Description
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SD/MMC Controller
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cv_5v4
2016.10.28
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