Altera cyclone V Technical Reference page 42

cv_5v4
2016.10.28
Each PLL has the following features:
• Phase detector and output lock signal generation
• Registers to set VCO frequency
• (M) Multiplier range is 1 to 4096
• (N) Divider range is 1 to 64
• Six post-scale counters (C0-C5) with a range of 1 to 512
• PLL can be enabled to bypass all outputs to the
The SDRAM PLL has the following additional feature:
• Phase shift of 1/8 per step
• Phase shift range is 0 to 7
Related Information
Cyclone V Device Datasheet
FREF, FVCO, and FOUT Equations
Figure 2-2: PLL Block Diagram
Values listed for M, N, and C are actually one greater than the values stored in the CSRs.
F
N
IN
(1 - 64)
PLL Bypass Path
FREF = F
FVCO = F
FOUT = F
Table 2-2: FREF, FVCO, and FOUT Equation variables
Variable
FVC = VCO frequency
Clock Manager
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F
REF
PFD VCO
F
FB
M
(1 - 4096)
/ N
IN
× M = F × M/N
REF IN
/ (C × K) = F
VCO i REF
Value
osc1_clk
F
VCO
Phase Shift
(1/8 Per Step)
Phase Shift
(1/8 Per Step)
Phase Shift
(1/8 Per Step)
Phase Shift
(1/8 Per Step)
Phase Shift
(1/8 Per Step)
Phase Shift
(1/8 Per Step)
× M/ (C × K) = (F × M)/ (N × C
i IN
-
FREF, FVCO, and FOUT Equations
clock for glitch-free transitions
C0 Divide
(1 - 512) × K
C1 Divide
(1 - 512) × K
C2 Divide
(1 - 512) × K
C3 Divide
(1 - 512)
C4 Divide
(1 - 512)
C5 Divide
(1 - 512)
× K)
i
Description
2-5
F
OUT
0
CLKOUT0
1
F
OUT
0
CLKOUT1
1
F
OUT
0
CLKOUT2
1
F
OUT
0
CLKOUT3
1
F
OUT
0
CLKOUT4
1
F
OUT
0
CLKOUT5
1
Bypass
Multiplexer
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