Altera cyclone V Technical Reference page 554

7-106
SDMMC Register Descriptions
31 30
15 14
fn_mod Fields
Bit
1
wr
0
rd
SDMMC Register Descriptions
Registers associated with the SDMMC slave interface. This slave is used by the DMA controller built into
the SDMMC to access slaves attached to the L3/L4 Interconnect.
Offset:
0x2000
fn_mod_ahb
Controls how AHB-lite burst transactions are converted to AXI tranactions.
read_qos
on page 7-107
QoS (Quality of Service) value for the read channel.
write_qos
QoS (Quality of Service) value for the write channel.
fn_mod
on page 7-109
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod_ahb
Controls how AHB-lite burst transactions are converted to AXI tranactions.
Module Instance
l3regs
Altera Corporation
29 28 27 26
13 12 11 10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-106
on page 7-108
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
0xFF800000
21 20 19 18
5 4 3 2
Access
Register Address
0xFF844028
System Interconnect
cv_5v4
2016.10.28
17 16
1 0
wr rd
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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