Altera cyclone V Technical Reference page 191

4-48
gpio_config_reg1
Bit
14:10
encoded_id_pwidth_c
9:5
encoded_id_pwidth_b
4:0
encoded_id_pwidth_a
gpio_config_reg1
Reports settings of various GPIO configuration parameters
Module Instance
fpgamgrregs
Offset:
0x874
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Specifies the width of GPIO Port C. Ignored because
there is no Port C in the GPIO.
Value
0x7
0xb
Specifies the width of GPIO Port B. Ignored because
there is no Port B in the GPIO.
Value
0x7
0xb
Specifies the width of GPIO Port A. The value 11
represents the 12-bit width less one.
Value
0x7
0xb
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Width (less 1) of 8 bits
Width (less 1) of 12 bits
Description
Width (less 1) of 8 bits
Width (less 1) of 12 bits
Description
Width (less 1) of 8 bits
Width (less 1) of 12 bits
Base Address
0xFF706874
2016.10.28
Access Reset
RO 0x7
RO 0x7
RO 0xB
Register Address
FPGA Manager
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cv_5v4