Sd/Mmc Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

14-84

SD/MMC Controller Address Map and Register Definitions

In internal DMA controller mode, the application needs to depend on the descriptor close
interrupt instead of the data done interrupt.
Related Information
• Enumerated Card Stack
Refer to this section for more information on discovering removable MMC cards.
• www.jedec.org
For more information, refer to "Access to Boot Partition" in JEDEC Standard No. JESD84-A43,
available on the JEDEC website.
Alternative Boot Operation for eMMC Card Devices
•
Refer to this section for information about alternative boot operation steps.
SD/MMC Controller Address Map and Register Definitions
The address map and register definitions for the SD/MMC Controller consists of the following region:
• SD/MMC Module
SDMMC Module Address Map
Registers in the SD/MMC module
Base Address:
SDMMC Module
Register
ctrl on page 14-86
pwren on page 14-89
clkdiv on page 14-90
clksrc on page 14-91
clkena on page 14-92
tmout on page 14-93
ctype on page 14-94
blksiz on page 14-95
bytcnt on page 14-96
intmask on page 14-
96
cmdarg on page 14-100
cmd on page 14-101
resp0 on page 14-107
Altera Corporation
on page 14-43
0xFF704000
Offset Width Acces
0x0 32
0x4 32
0x8 32
0xC 32
0x10 32
0x14 32
0x18 32
0x1C 32
0x20 32
0x24 32
0x28 32
0x2C 32
0x30 32
†
on page 14-79
Reset Value
s
Control Register
RW 0x0
Power Enable Register
RW 0x0
Clock Divider Register
RW 0x0
SD Clock Source Register
RW 0x0
Clock Enable Register
RW 0x0
Timeout Register
RW 0xFFFFFF40
Card Type Register
RW 0x0
Block Size Register
RW 0x200
Byte Count Register
RW 0x200
Interrupt Mask Register
RW 0x0
Command Argument Register
RW 0x0
Command Register
RW 0x20000000
Response Register 0
RO 0x0
cv_5v4
2016.10.28
Description
SD/MMC Controller
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