Altera cyclone V Technical Reference page 222

5-28
hpsinfo
Bit
2:0
bsel
hpsinfo
Provides information about the HPS capabilities.
Module Instance
sysmgr
Offset:
0x18
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
The boot select field specifies the boot source. It is
read by the Boot ROM code on a cold or warm reset
to determine the boot source. The HPS BSEL pins
value are sampled upon deassertion of cold reset.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Description
Reserved
FPGA (HPS2FPGA Bridge)
NAND Flash (1.8v)
NAND Flash (3.0v)
SD/MMC External Transceiver (1.8v)
SD/MMC Internal Transceiver (3.0v)
QSPI Flash (1.8v)
QSPI Flash (3.0v)
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Access
Register Address
0xFFD08018
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
Reset
RO 0x0
17 16
1 0
can dualcore
RO RO 0x0
0x0
System Manager
Send Feedback