Multi-Port Front End - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Figure 11-2: SDRAM Controller Block Diagram
FPGA
Fabric

Multi-Port Front End

The Multi-Port Front End (MPFE) is responsible for scheduling pending transactions from the configured
interfaces and sending the scheduled memory transactions to the single-port controller. The MPFE
handles all functions related to individual ports.
The MPFE consists of three primary sub-blocks.
Command Block
The command block accepts read and write transactions from the FPGA fabric and the HPS. When the
command FIFO buffer is full, the command block applies backpressure by deasserting the ready signal.
For each pending transaction, the command block calculates the next SDRAM burst needed to progress
on that transaction. The command block schedules pending SDRAM burst commands based on the
user-supplied configuration, available write data, and unallocated read data space.
SDRAM Controller Subsystem
Send Feedback
Multi-Port Front End
Read Data
6
Data
Reorder
FIFO
Buffer
Buffers
Write Data
6
FIFO
Data
POP
FIFO
Logic
Buffers
Command
6 Write
WR Acknowledge
Acknowledge Queues
10
Command
Scheduler
FIFO
Buffers
SDRAM Controller
Write Data
Buffer
Command
Generator
Control & Status Register Interface
Multi-Port Front End
Single-Port Controller
ECC
Generation
&
Checking
Rank Timer
Timer
Bank Arbiter
Pool
Altera Corporation
11-7
Altera
PHY
Interface