Instructions - Altera cyclone V Technical Reference

Hard processor system
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cv_5v4
2016.10.28
Mnemonic
DMAGO
DMAKILL
DMALD
DMALDP
DMALP
DMALPEND
DMALPFE
DMAMOV
DMANOP
DMARMB
DMASEV
DMAST
DMASTP
DMASTZ
DMAWFE
DMAWFP
DMAWMB

Instructions

DMA Controller
Send Feedback
Instruction
DMA Manager
Go
Yes
Kill
Yes
Load
No
Load and Notify
No
Peripheral
Loop
No
Loop End
No
Loop Forever
No
Move
No
No Operation
Yes
Read Memory
No
Barrier
Send Event
Yes
Store
No
Store and Notify
No
Peripheral
Store Zero
No
Wait For Event
Yes
Wait For
No
Peripheral
Write Memory
No
Barrier
DMA Channel
Usage
Usage
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
16-35
Instructions
Description
DMAGO
on page 16-38
DMAKILL
on page 16-
39
DMALD[S | B]
on page
16-40
DMALDP<S | B>
on page
16-40
DMALP
on page 16-41
DMALPEND[S | B]
on
page 16-42
DMALPFE
on page 16-
44
DMAMOV
on page 16-
44
DMANOP
on page 16-
45
DMARMB
on page 16-
45
DMASEV
on page 16-46
DMAST[S | B]
on page
16-46
DMASTP<S | B>
on page
16-47
DMASTZ
on page 16-48
DMAWFE
on page 16-
48
DMAWFP
on page 16-
49
DMAWMB
on page 16-
50
Altera Corporation

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