Altera cyclone V Technical Reference page 244

5-50
DMA Controller Group Register Descriptions
Bit
3:0
arcache_0
DMA Controller Group Register Descriptions
Registers used by the DMA Controller to enable secured system support and select DMA channels.
Offset:
0x70
ctrl
on page 5-51
Registers used by the DMA Controller. All fields are reset by a cold or warm reset. These register bits
should be updated during system initialization prior to removing the DMA controller from reset. They
may not be changed dynamically during DMA operation.
persecurity
Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits
from reset. These register bits should be updated during system initialization prior to removing the DMA
controller from reset. They may not be changed dynamically during DMA operation.
Altera Corporation
Name
Specifies the values of the 2 EMAC ARCACHE
signals. The field array index corresponds to the
EMAC index.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
on page 5-52
Description
Description
Noncacheable and nonbufferable.
Bufferable only.
Cacheable, but do not allocate.
Cacheable and bufferable, but do not allocate.
Reserved.
Reserved.
Cacheable write-through, allocate on reads
only.
Cacheable write-back, allocate on reads only.
Reserved.
Reserved.
Cacheable write-through, allocate on writes
only.
Cacheable write-back, allocate on writes only.
Reserved.
Reserved.
Cacheable write-through, allocate on both
reads and writes.
Cacheable write-back, allocate on both reads
and writes.
cv_5v4
2016.10.28
Access Reset
RW 0x0
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