Altera cyclone V Technical Reference page 750

11-12
MPFE Multi-Port Arbitration
Setting the MPFE Static Weights
The static weight settings used in the round-robin command port priority scheme are programmed in a
128-bit field distributed among four 32-bit registers:
•
mpweight_0_4
•
mpweight_1_4
•
mpweight_2_4
•
mpweight_3_4
Each port is assigned a 5-bit value within the 128-bit field, such that port 0 is assigned to bits [4:0] of the
mpweight_0_4
assigned to bits[49:45] contained in the
to 0x1F, with larger static weights representing a larger arbitration share.
Bits[113:50] in the
for each priority. This 64-bit field is divided into eight fields of 8-bits, each representing the sum of static
weights. Bits[113:50] are mapped in ascending order with bits [57:50] holding the sum of static weights for
all ports with priority setting 0x0, and bits [113:106] holding the sum of static weights for all ports with
priority setting 0x7.
Example Using MPFE Priority and Weights
In this example, the following settings apply:
• FPGA MPFE ports 0 is assigned to AXI read commands and port 1 is assigned to AXI write
commands.
• FPGA MPFE port 2 is assigned to Avalon-MM read and write commands.
• L3 master ports (ports 6 and 8) and the MPU ports (port 7 and 9) are given the lowest priority but the
MPU ports are configured with more arbitration static weight than the L3 master ports.
• The FPGA MPFE command ports are given the highest priority; however, AXI ports 0 and 1 are given a
larger static weight because they carry the highest priority traffic in the entire system. Assigning a high
priority and larger static weight ensures ports 0 and 1 will receive the highest quality-of-service (QoS).
The table below details the port weights and sum of weights.
Table 11-5: SDRAM MPFE Port Priority, Weights and Sum of Weights
Priority
-
1
0
If the FPGA-to-SDRAM ports are configured according to the table and if both ports are accessed
concurrently, you can expect the AXI port to receive 80% of the total service. This value is determined by
taking the sum of port 0 and 1 weights divided by the total weight for all ports of priority 1. The remaining
20% of bandwidth is allocated to the Avalon-MM port. With these port settings, any FPGA transaction
buffered by the MPFE for either slave port blocks the MPU and L3 masters from having their buffered
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register, port 1 is assigned to bits [9:5] of the
,
mpweight_1_4 mpweight_2_4
Port Port
0 1
10 10
0 0
mpweight_0_4
register. The valid weight range for each port is 0x0
mpweight_1_4
and
mpweight_3_4
Weights
Port Port Port Port
2 3 4 5
5 0 0 0
0 0 0 0
register up to port 9, which is
registers, hold the sum of weights
Port Port Port Port
6 7 8 9
0 0 0 0
1 4 1 4
SDRAM Controller Subsystem
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cv_5v4
2016.10.28
Sum of
Weights
-
25
10