Altera cyclone V Technical Reference page 966

14-20
PBL and Watermark Levels
For transmit:
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• PBL=4
• TX watermark = 1
For these programming values, if the FIFO buffer has only one location empty, the DMA attempts to read
four words from memory even though there is only one word of storage available. This results in a FIFO
Buffer Overflow interrupt.
For receive:
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• PBL=4
• RX watermark = 1
For these programming values, if the FIFO buffer has only one location filled, the DMA attempts to write
four words, even though only one word is available. This results in a FIFO Buffer Underflow interrupt.
The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a
multiple of four bytes. For example, if the
descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes.
PBL and Watermark Levels
This table shows legal PBL and FIFO buffer watermark values for internal DMA controller data transfer
operations.
Table 14-10: PBL and Watermark Levels
PBL (Number of transfers)
CIU
The Card Interface Unit (CIU) interfaces with the BIU and SD/MMC cards or devices. The host processor
writes command parameters to the SD/MMC controller's BIU control registers and these parameters are
then passed to the CIU. Depending on control register values, the CIU generates SD/MMC command and
data traffic on the card bus according to the SD/MMC protocol. The control register values also decide
whether the command and data traffic is directed to the CE-ATA card, and the SD/MMC controller
controls the command and data path accordingly.
Altera Corporation
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1
4
8
16
32
64
128
256
register = 13, the number of bytes indicated in the
bytcnt
TX/RX FIFO Buffer Watermark Value
greater than or equal to 1
greater than or equal to 4
greater than or equal to 8
greater than or equal to 16
greater than or equal to 32
greater than or equal to 64
greater than or equal to 128
greater than or equal to 256
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cv_5v4
2016.10.28
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SD/MMC Controller
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