STMicroelectronics SPC572L series Reference Manual

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SPC572Lx - 32-bit Power Architecture® based MCU for automotive

Introduction

Overview

This document defines the functionality of the SPC572Lx microcontroller for use by software

and hardware developers. The SPC572Lx is built on Power Architecture® technology and

integrates technologies that are important for today's and tomorrow's automotive

applications, including automotive powertrain controller applications for four-cylinder

gasoline and diesel engines, chassis control applications, transmission control applications,

steering and braking applications, as well as low-end hybrid applications and safety

applications that require a high safety integrity level.

The information in this book is subject to change without notice, as described in the

disclaimer. As with any technical documentation, it is the reader's responsibility to be sure

he or she is using the most recent version of the documentation.

To locate any published errata or updates for this document, visit the ST Web site at

http://www.st.com.

Audience

This manual is intended for system software and hardware developers and applications

programmers who want to develop products with the SPC572Lx device. It is assumed that

the reader understands operating systems, microprocessor system design, basic principles

of software and hardware, and basic details of the Power Architecture.

Document organization

This document includes chapters that are divided into parts:

•

Part I includes chapters that describe the device as a whole or provide device-specific

information.

•

Part II includes chapters that describe the functionality of the individual modules on the

device.

September 2017

DocID027809 Rev 4

RM0400

Reference manual

powertrain applications

1/2058

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Summary of Contents for STMicroelectronics SPC572L series

Page 1 RM0400 Reference manual SPC572Lx - 32-bit Power Architecture® based MCU for automotive powertrain applications Introduction Overview This document defines the functionality of the SPC572Lx microcontroller for use by software and hardware developers. The SPC572Lx is built on Power Architecture® technology and integrates technologies that are important for today’s and tomorrow's automotive applications, including automotive powertrain controller applications for four-cylinder gasoline and diesel engines, chassis control applications, transmission control applications,...
Page 2: Table Of Contents
Contents RM0400 Contents Preface ........... 91 Overview .
Page 3 RM0400 Contents Package pinouts ......... . . 105 Pin descriptions .
Page 4 Contents RM0400 6.6.1 Software Watchdog Timer (SWT) configuration ....156 6.6.2 PIT configuration ......... 157 6.6.3 GTM integration module configuration .
Page 5 RM0400 Contents 7.3.5 PHASE2: flash initial configuration ......191 7.3.6 PHASE3: device configuration ....... 191 7.3.7 IDLE Phase .
Page 6 Contents RM0400 9.6.2 Power-down sequence ........235 9.6.3 Brown-out management .
Page 7 RM0400 Contents 12.6.4 Interrupt Vector Prefix Registers (IVPR) ..... . . 273 12.6.5 Interrupt Definitions ........274 System Integration Unit Lite2 (SIUL2) .
Page 8 Contents RM0400 15.3.1 Access support ......... . 324 System Memory Protection Unit (SMPU) .
Page 9 RM0400 Contents 18.6.2 Priority management ........368 18.6.3 Handshaking with processor .
Page 10 Contents RM0400 19.3.15 Hardware Request Status Register Low (DMA_HRSL) ... . 413 19.3.16 Channel n Priority Register (DMA_DCHPRIn) ....415 19.3.17 Channel n Master ID Register (DMA_DCHMIDn) .
Page 11 RM0400 Contents 19.5.7 Dynamic programming ........447 Direct Memory Access Multiplexer (DMAMUX) .
Page 12 Contents RM0400 21.7 Clock monitoring ......... . . 474 21.7.1 CMU configuration .
Page 13 RM0400 Contents 23.5.3 CLKMN1 supervisor ........493 Clock Generation Module (MC_CGM) .
Page 14 Contents RM0400 27.4.1 Read / Write introduction ........553 27.4.2 Initialization/application information .
Page 15 RM0400 Contents 29.4.1 Reset ..........629 29.4.2 Power-down mode (Disable mode) .
Page 16 Contents RM0400 31.8.6 Planning factory test mode disable ......673 Error Reporting Module (ERM) ....... 674 32.1 Introduction .
Page 17 RM0400 Contents 35.4.1 Differential input mode ........734 35.4.2 Single-ended input mode .
Page 18 Contents RM0400 36.4.6 Programmable analog watchdog ......764 36.4.7 DMA functionality ......... 765 36.4.8 Interrupts .
Page 19 RM0400 Contents 37.4.13 Integrator ..........836 37.5 Initialization Information .
Page 20 Contents RM0400 40.4 Functional description ........857 Periodic Interrupt Timer (PIT) .
Page 21 RM0400 Contents 42.6.3 GTMDI reset configuration ........944 42.6.4 Message Data Bus —interface with NAR module .
Page 22 Contents RM0400 44.3.3 Dual clock sources ........1001 44.3.4 Dual interrupt lines .
Page 23 RM0400 Contents 45.6.1 External signals ......... 1095 45.6.2 Frame format .
Page 24 Contents RM0400 46.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe ............1139 46.2.5 PCS[6] –...
Page 25 RM0400 Contents 46.3.27 DSPI DSI Deserialized Data Polarity Interrupt Register 1 (DSPI_DPIR1) ............1176 46.3.28 DSPI Clock and Transfer Attributes Register Extended (DSPI_CTAREn) .
Page 26 Contents RM0400 47.6.1 Memory map ......... . . 1225 47.6.2 Register descriptions .
Page 27 RM0400 Contents 48.4.6 MII Management Frame Register (MMFR) ....1307 48.4.7 MII Speed Control Register (MSCR) ......1309 48.4.8 MIB Control Register (MIBC) .
Page 28 Contents RM0400 48.4.42 Count of transmitted frames not counted correctly (IEEE_T_DROP) 1326 48.4.43 Frames transmitted OK (IEEE_T_FRAME_OK) ....1326 48.4.44 Frames transmitted with single collision (IEEE_T_1COL) ..1326 48.4.45 Frames transmitted with multiple collisions (IEEE_T_MCOL) .
Page 29 RM0400 Contents 48.4.78 Octet count for frames received without error (IEEE_R_OCTETS_OK) ............1338 48.5 Functional description .
Page 30 Contents RM0400 49.4.2 DMA read logic ......... 1398 49.4.3 Message reading via interrupts .
Page 31 RM0400 Contents Reset Generation Module (MC_RGM) ......1507 51.1 Introduction ..........1507 51.1.1 Overview .
Page 32 Contents RM0400 53.3 Memory map and register definition ......1561 53.3.1 Register descriptions ........1562 53.4 Functional description .
Page 33 RM0400 Contents 56.1.3 Modes of operation ........1599 56.2 External signal description .
Page 34 Contents RM0400 57.3.2 Debug Control and Status registers ......1657 57.3.3 External Debug Resource Allocation Control (EDBRAC0) register . . 1676 57.3.4 Debug Event Select register (DEVENT) register .
Page 35 RM0400 Contents 59.2.2 TDI—Test data input ........1733 59.2.3 TDO—Test data output .
Page 36 Contents RM0400 60.5.2 Resets ..........1750 60.5.3 Start-up Options .
Page 37 RM0400 Contents 62.2 Functional description ........1804 62.2.1 Module architecture .
Page 38 Contents RM0400 64.3.1 DTS register access ........1867 64.4 Memory map and register definition .
Page 39 RM0400 Contents e200z215An3 Nexus 3 Module ......1909 66.1 Introduction ..........1909 66.1.1 General Description .
Page 40 Contents RM0400 66.8.3 Message Suppression ........1946 66.8.4 Nexus Message Priority .
Page 41 RM0400 Contents 66.17.1 Single write access ........1969 66.17.2 Block write access .
Page 42 Contents RM0400 68.1.1 Overview ..........1994 68.1.2 Features .
Page 43 RM0400 Contents Appendix A Acronyms and abbreviations ......2024 Revision history ..........2028 DocID027809 Rev 4 43/2058...
Page 44 List of tables RM0400 List of tables Table 1. Register conventions ........... . . 92 Table 2.
Page 45 RM0400 List of tables Table 49. LINFlexD configurations ..........169 Table 50.
Page 46 List of tables RM0400 Table 101. Data Storage Interrupt—register settings ........275 Table 102.
Page 47 RM0400 List of tables Table 153. Operation modes available ..........345 Table 154.
Page 48 List of tables RM0400 Table 205. Coherency model for method 2 ..........449 Table 206.
Page 49 RM0400 List of tables Table 255. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) field descriptions ..516 Table 256. Auxiliary Clock 3 Select Status Register (CGM_AC3_SS) field descriptions ..517 Table 257.
Page 50 List of tables RM0400 Table 302. LOCK1 field descriptions ..........612 Table 303.
Page 51 RM0400 List of tables Table 354. SAR ADC4 register definitions ..........728 Table 355.
Page 52 List of tables RM0400 Table 406. TCJCMR field descriptions ..........793 Table 407.
Page 53 RM0400 List of tables Table 457. GTMDI signal properties ..........877 Table 458.
Page 54 List of tables RM0400 Table 509. Watchpoint field WPHIT[11:0] format for WPHIT[14:12] = 0b001 ....948 Table 510. Watchpoint field WPHIT[11:0] format for WPHIT[14:12] = 0b010 ....948 Table 511.
Page 55 RM0400 List of tables Table 561. TXBCR field descriptions ..........1042 Table 562.
Page 56 List of tables RM0400 Table 613. DSPI SCK duty cycle ........... 1150 Table 614.
Page 57 RM0400 List of tables Table 665. RFCR field descriptions ..........1238 Table 666.
Page 58 List of tables RM0400 Table 717. TFWR field descriptions ..........1317 Table 718.
Page 59 RM0400 List of tables Table 769. RMON_R_P_GTE2048 field descriptions........1335 Table 770.
Page 60 List of tables RM0400 Table 821. Slave node – Rx mode — Register setting ........1448 Table 822.
Page 61 RM0400 List of tables Table 871. MC_RGM reset implications ..........1536 Table 872.
Page 62 List of tables RM0400 Table 923. Mode Enable Register (ME_ME) field descriptions ......1608 Table 924.
Page 63 RM0400 List of tables Table 975. Reset effects ............1753 Table 976.
Page 64 List of tables RM0400 Table 1027. SE register field descriptions ..........1844 Table 1028.
Page 65 RM0400 List of tables Table 1079. PCR field descriptions ..........1921 Table 1080.
Page 66 List of tables RM0400 Table 1131. CIN register field descriptions ..........1999 Table 1132.
Page 67 RM0400 List of figures List of figures Figure 1. Key to register fields ............91 Figure 2.
Page 68 List of figures RM0400 Figure 49. Exception Syndrome Register (ESR) ........268 Figure 50.
Page 69 RM0400 List of figures Figure 99. Write, pending read (2:1 timing mode) ........349 Figure 100.
Page 70 List of figures RM0400 Figure 147. TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) ..........425 Figure 148.
Page 71 RM0400 List of figures Figure 196. Auxiliary Clock 0 Divider 0 Configuration Register (CGM_AC0_DC0) ....510 Figure 197. Auxiliary Clock 0 Divider 1 Configuration Register (CGM_AC0_DC1) ....511 Figure 198.
Page 72 List of figures RM0400 Figure 249. PFlash calibration remap connection matrix ........583 Figure 250.
Page 73 RM0400 List of figures Figure 301. Error Injection Channel n Descriptor, Word1 (EICHDn.Word1) ....689 Figure 302. Error Injection Channel n Descriptor, Word2 (EICHDn.Word2) ....690 Figure 303.
Page 74 List of figures RM0400 Figure 353. Test Channel Injected Conversion Mask Register (TCJCMR) ..... 793 Figure 354. Test Channels Watchdog Select Registers 0–3 (TCWSELR0–TCWSELR3)..794 Figure 355.
Page 75 RM0400 List of figures Figure 405. Watchpoint triggers and watchpoint messages ....... . 874 Figure 406.
Page 76 List of figures RM0400 Figure 450. TBU2 watchpoint control 2 register (GTMDI_TBU2_WPC2) ..... . 940 Figure 451. TBU2 watchpoint DATA register (GTMDI_TBU2_DATA) ......942 Figure 452.
Page 77 RM0400 List of figures Figure 502. Tx Buffer Configuration register ......... . . 1038 Figure 503.
Page 78 List of figures RM0400 Figure 554. Streaming transfer with data ..........1105 Figure 555.
Page 79 RM0400 List of figures Figure 606. DSPI DSI Transmit Comparison Register 1 (DSPI_COMPR1)....1174 Figure 607. DSPI DSI Deserialization Data Register 1 (DSPI_DDR1) ..... . . 1174 Figure 608.
Page 80 List of figures RM0400 Figure 658. Ping Status Register (PISR) ..........1247 Figure 659.
Page 81 RM0400 List of figures Figure 710. Receive Descriptor Ring Start Register (ERDSR) ......1318 Figure 711.
Page 82 List of figures RM0400 Figure 762. Frames received OK (IEEE_R_FRAME_OK) ....... . . 1336 Figure 763.
Page 83 RM0400 List of figures Figure 814. Incomplete response (for example, missing checksum) ......1422 Figure 815. No response ............1423 Figure 816.
Page 84 List of figures RM0400 Figure 866. Global Control Register (GCR) ..........1488 Figure 867.
Page 85 RM0400 List of figures Figure 918. SEC_SWT_CPU bit configuration ......... 1548 Figure 919.
Page 86 List of figures RM0400 Figure 970. HALT0 Mode Configuration Register (ME_HALT0_MC) ......1618 Figure 971. STOP0 Mode Configuration Register (ME_STOP0_MC) ......1619 Figure 972.
Page 87 RM0400 List of figures Figure 1022.Device identification register ..........1735 Figure 1023.JTAG_PASSWORD register.
Page 88 List of figures RM0400 Figure 1074.C2PEVP register format ..........1829 Figure 1075.C2PIS register format .
Page 89 RM0400 List of figures Figure 1126.Shifting data into register ..........1903 Figure 1127.Nexus command format for register selection .
Page 90 List of figures RM0400 Figure 1178.Data Trace — Data Write message ........1965 Figure 1179.Data Trace —...
Page 91: Preface
RM0400 Preface Preface Overview This document defines the functionality of the SPC572Lx microcontroller for use by software ® and hardware developers. The SPC572Lx is built on Power Architecture technology and integrates technologies that are important for today’s and tomorrow's automotive applications, including automotive powertrain controller applications for four-cylinder gasoline and diesel engines, chassis control applications, transmission control applications, steering and braking applications, as well as low-end hybrid applications and safety...
Page 92: Acronyms And Abbreviations
Preface RM0400 Table 1. Register conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register field types Read only.
Page 93: Introduction
RM0400 Introduction Introduction SPC572Lx microcontroller The SPC572Lx microcontroller is a new member in a family of devices building on the legacy of the superseded SPC56xx family while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW).
Page 94 Introduction RM0400 peripherals are connected at either 80 MHz or 40 MHz depending on their need. The reduced speed for the peripherals helps to reduce power. 94/2058 DocID027809 Rev 4...
Page 95: Features Summary
RM0400 Introduction Features summary On-chip modules within SPC572Lx include the following features: • 1 main CPU, single issue, 32-bit CPU core complex (e200z2) – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction –...
Page 96: Feature List
Introduction RM0400 • Fast Ethernet Controller (FEC) • Fast Asynchronous Serial Transmission (LFAST) • Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard • Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and IEEE 1149.7) •...
Page 97: Packaging
RM0400 Introduction Table 2. SPC572L64 device feature summary(Continued) Feature Description SENT bus Ethernet SIPI / LFAST Interprocessor bus High speed (4-phase only) 4 PIT channels ® System timers 1 AUTOSAR (STM) 64-bit PIT 16 input channels, GTM timer 56 output channels GTM RAM 18.53 KB Interrupt controller...
Page 98: Block Diagrams
Introduction RM0400 Block diagrams Figure 2. Block diagram DCI (without JTAGM JTAGC LFAST support) SWT_3 DMA CH MUX SWT_2 INTC_2 STM_2 LFAST Ethernet & SIPI 16ch eDMA e200z215An3–80 MHz 40 MHz Core Nexus 3 Scalar SP-FPU Concentrator 40 MHz Load/Store Instruction 32 ADD 32 ADD...
Page 99: Figure 3. Periphery Allocation
RM0400 Introduction Figure 3. Periphery allocation SSCM PBRIDGE_A PASS XBAR_0 Flash control SMPU_0 LFAST_0 PRAM_0 SIPI_0 SIUL2 PFLASH_0 MC_ME INTC_0 MC_CGM SWT_2 CMU_PLL SWT_3 PLLDIG STM_2 XOSC DMA_0 IRCOSC FEC_0 MC_RGM PMCDIG MC_PCU WKPU SAR ADC_0 DECIFILTER SAR ADC_4 PIT_0 SAR ADC_B PIT_1 Peripheral Bus A...
Page 100: Embedded Memories
Embedded memories RM0400 Embedded memories Overview The embedded memory architecture for SPC572Lx devices is a significant departure from previous-generation devices. Features include: • Onboard system SRAM and overlay SRAM • Onboard system error correction code (ECC) flash memory • Embedded memories in the peripherals –...
Page 101: Processor Core Local Sram
RM0400 Embedded memories The calibration remap function supports two different types of overlay SRAM: • An internal overlay RAM is included on all standard production devices. • A portion of the system RAM can be used as the overlay RAM. The overlay function is implemented using registers in the flash memory controller.
Page 102: Flash Memory Controller
Embedded memories RM0400 Figure 4. SPC572Lx flash memory block diagram XBAR Flash Memory Controller 4-Entry, 2-Way Mini-Cache 128 Read 64 Write 1.5 MB Flash Memory Array The remaining sections give the functional details of the flash controller and flash array, followed by the memory maps.
Page 103 RM0400 Embedded memories 3.3.2.1 Features • Flash segmentation – 256 KB blocks provided for code or data – Two 16 KB blocks provided for EEPROM emulation – Support for reading-while-writing when the accesses are to different partitions • Flash memory protection: write protection and OTP function available for each block •...
Page 104: Security Features
Embedded memories RM0400 Figure 5. Flash memory segmentation and read-while-write partitioning Read Partition 0 Read Partition 1 8 KB UTEST Low Address 8 KB BAF Space 16 KB (block 0) 16 KB (block 1) High Address Space 2 x 16 KB EEPROM emulation 256 KB Address 6 x 256 KB...
Page 105: Signal Description
RM0400 Signal description Signal description Production packages The following production packages are for the SPC572Lx device: • eTQFP80 • eTQFP100 Case number and outline drawings for each package are provided in the SPC572Lx data sheet. Package pinouts For package pinouts refer to the SPC572Lx data sheet. Pin descriptions The following sections provide signal descriptions and related information about the functionality and configuration of the SPC572Lx device.The signal multiplexing options...
Page 106: Power Supply And Reference Voltage Pins
Signal description RM0400 2. Pins on the device that are not supply or reference are not explicilty defined in this table. 3. Pure analog inputs, on digital output function. 4. Device does not implement system configuration pin. TESTMODE is the only pin affecting device configuration. It is latched on PORST rising edge and internally pull-down.
Page 107: Lvds Pins
RM0400 Signal description Table 5. System pins QFP pin Symbol Description Direction Power on reset with Schmitt trigger characteristics PORST Bidirectional and noise filter. PORST is active low External functional reset with Schmitt trigger ESR0 Bidirectional characteristics and noise filter. ESR0 is active low Pin for testing purpose only.
Page 108: Generic Pins
Signal description RM0400 Table 6. LVDSM pin descriptions(Continued) Package pin number Functional Port Signal Signal description Direction eTQFP80 eTQFP100 block DSPI 4 Microsecond Bus Serial PD[3] SCK_N Clock, LVDS Negative Terminal DSPI 4 Microsecond Bus Serial PD[2] SCK_P DSPI 4 Clock, LVDS Positive Terminal Microsecond DSPI 4 Microsecond Bus Serial...
Page 109: Memory Map
RM0400 Memory map Memory map Table 7 shows the device memory map for the SPC572Lx. All addresses on the SPC572Lx, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each region or module name.
Page 110 Memory map RM0400 Table 8. Peripheral (PBRIDGE_A) memory map(Continued) PBRIDGE Allocated Used Access Start address End address Description size size Control Register 0xFC008000 0xFC00FFFF — Reserved System Memory Protection Unit 0 0xFC010000 0xFC013FFF 16 KB — PACR4 (SMPU_0) 0xFC014000 0xFC01FFFF —...
Page 111 RM0400 Memory map Table 8. Peripheral (PBRIDGE_A) memory map(Continued) PBRIDGE Allocated Used Access Start address End address Description size size Control Register 0xFFE5C000 0xFFE5FFFF 16 KB — PCTL104 SENT (SAE J2716) Receiver 0 (SRX_0) 0xFFE60000 0xFFE6FFFF — Reserved Deserial Serial Peripheral Interface 0 0xFFE70000 0xFFE73FFF 16 KB...
Page 112 Memory map RM0400 Table 8. Peripheral (PBRIDGE_A) memory map(Continued) PBRIDGE Allocated Used Access Start address End address Description size size Control Register 0xFFF80000 0xFFF83FFF 16 KB — PCTL31 Periodic Interrupt Timer 1 (PIT_1) 0xFFF84000 0xFFF87FFF 16 KB — PCTL30 Periodic Interrupt Timer 0 (PIT_0) 0xFFF88000 0xFFF8BFFF 16 KB...
Page 113: Table 9. Flash Memory And Overlay Ram Map
RM0400 Memory map Table 8. Peripheral (PBRIDGE_A) memory map(Continued) PBRIDGE Allocated Used Access Start address End address Description size size Control Register Password and Device Security Module 0xFFFF4000 0xFFFF7FFF 16 KB — PCTL2 (PASS) System Status and Configuration 0xFFFF8000 0xFFFFBFFF 16 KB —...
Page 114: Table 10. Ram Memory Map
Memory map RM0400 Table 9. Flash memory and overlay RAM map(Continued) Complete flash memory Allocated Block Start address End address size partition size block structure 0x090C0000 0x090FFFFF 256 KB 256 KB Flash block3 256 KB 0x09100000 0x0913FFFF 256 KB 256 KB Flash block4 256 KB 0x09140000 0x0917FFFF...
Page 115 Wafer lot, X/Y-position on the wafer, 0x004000A0 0x004000BF Unique Identifier (UID) manufacturing data, test results, flash firmware ID and parameters, company ID: 66 = STMicroelectronics 0x004000C0 0x004000FF — Reserved Protected from read operations flash BIU from Production at Life Cycle.
Page 116 Memory map RM0400 Table 11. UTEST flash memory map(Continued) Allocated Start address End address size Description Comments [bytes] 0x00400120 0x0040013F JTAG Password Protected from read operations 0x00400140 0x0040015F PASS Password Group 0 flash BIU from Production at 0x00400160 0x0040017F PASS Password Group 1 0x00400180 0x0040019F PASS Password Group 2...
Page 117: Device Configuration
RM0400 Device configuration Device configuration Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device • specific module-to-module interactions not necessarily discussed in the individual module chapters •...
Page 118 Device configuration RM0400 Table 12. Reset settings for e200z215An3 resources(Continued) Resource System reset setting DBSR 0x1000_0000 DDAM 0x0000_0000 DDEAR Unaffected DEAR Unaffected DEVENT 0x0000_0000 DSRR0 Unaffected DSRR1 Unaffected DVC1 Unaffected DVC2 Unaffected 0x0000_0000 HID0 0x0000_0000 HID1 0x0000_0000 IAC1 0x0000_0000 IAC2 0x0000_0000 IAC3 0x0000_0000...
Page 119: Special Purpose Register (Spr) Summary
RM0400 Device configuration Table 12. Reset settings for e200z215An3 resources(Continued) Resource System reset setting PID0 0x0000_0000 0x0000_00 || p_cpuid[0:7] — SPEFSCR 0x0000_0000 SPRG0 Unaffected SPRG1 Unaffected SPRG2 Unaffected SPRG3 Unaffected SRR0 Unaffected SRR1 Unaffected — 0x0000_0000 1. The levels that determine these bits are set by the factory and may change between revisions of the device.
Page 120 Device configuration RM0400 Table 13. Special purpose registers(Continued) e200z Mnemonic Name Access Privileged number specific Exception Syndrome Register IVPR Interrupt Vector Prefix Register User SPR General 0 USPRG0 (VRSAVE) (renamed to VRSAVE in PowerISA 2.06) SPRG0 SPR General 0 SPRG1 SPR General 1 SPRG2 SPR General 2...
Page 121 RM0400 Device configuration Table 13. Special purpose registers(Continued) e200z Mnemonic Name Access Privileged number specific MCSRR1 Machine Check Save/Restore Register 1 Read/Clear MCSR Machine Check Syndrome Register MCAR Machine Check Address Register DSRR0 Debug save/restore register 0 DSRR1 Debug save/restore register 1 DDAM Debug Data Acquisition Messaging register DAC3...
Page 122: System Modules
Device configuration RM0400 System modules 6.3.1 SIUL2 configuration The System Integration Unit Lite 2 (SIUL2) controls the MCU pad configuration, ports, general-purpose input and output (GPIO) signals and external interrupts with trigger event configuration. For details please refer Chapter 13: System Integration Unit Lite2 (SIUL2).
Page 123: System Memory Protection Unit (Smpu) Configuration
RM0400 Device configuration Table 14. Reference links to related information Topic Related module Reference Full description Crossbar switch Chapter 14: Crossbar Switch (XBAR) System memory map — Chapter 5: Memory map Clocking — Chapter 21: Clocking Crossbar switch master Core Section 6.2: Core module Crossbar switch slave Flash memory controller...
Page 124: Table 17. Reference Links To Related Information
Device configuration RM0400 6.3.3.1 SMPU_0 configuration This section summarizes how the module is configured in the chip. For a comprehensive description of the SMPU module itself, see the module’s dedicated chapter. Figure 7. SMPU_0 configuration Table 17. Reference links to related information Topic Related module Reference...
Page 125: Peripheral Bridge Configuration
RM0400 Device configuration Table 18. SMPU_0 logical bus master assignments SMPU logical bus master number Bus master Core Reserved Reserved Ethernet Reserved Reserved SIPI/LFAST Core Debug Reserved Reserved Reserved Reserved Reserved Reserved Reserved 6.3.3.1.2 Number of region descriptors supported by SMPU_0 This instance of the SMPU module supports up to 12 region descriptors.
Page 126: Platform Configuration Module (Pcm)
Device configuration RM0400 Table 19. Reference links to related information Topic Related module Reference Full description Peripheral bridge Chapter 15: Peripheral Bridge System memory map — Chapter 5: Memory map Clocking — Chapter 21: Clocking Crossbar switch Crossbar switch Section 6.3.2: Crossbar switch configuration 6.3.4.1 Memory maps The peripheral bridge is used to access the registers of most of the modules on this device.
Page 127: Interrupt Controller (Intc) Configuration
RM0400 Device configuration Table 20. IAHB_BE2 field descriptions Field Description 0–4 Reserved 5–7 Reserved, undefined 8–12 Reserved 13–15 Reserved, undefined 16–20 Reserved 21–23 Reserved, undefined 24–28 Reserved Pending read enable (PRE) M2 This bit controls the bus gasket’s handling of pending read transactions. PRE_M2 0 Pending reads are disabled.
Page 128: Table 22. Interrupt Sources
Device configuration RM0400 Table 21. INTC implemented registers(Continued) Address offset Register 034h Reserved 038h Reserved INTC Software Set/Clear Interrupt Register 0 (INTC_SSCIR0) – 040h–05Ch INTC Software Set/Clear Interrupt Register 31 (INTC_SSCIR31) INTC Priority Select Register 0 (INTC_PSR0) – 05Ch–85Ch INTC Priority Select Register 1023 (INTC_PSR1023) 6.3.6.2 Interrupt sources Table 22...
Page 129 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name 105Ch Software settable flag 23 SSCIR20_23[CLR23] 1060h Software settable flag 24 SSCIR24_27[CLR24] 1064h Software settable flag 25 SSCIR24_27[CLR25] 1068h Software settable flag 26 SSCIR24_27[CLR26] 106Ch Software settable flag 27 SSCIR24_27[CLR27] 1070h Software settable flag 28 SSCIR28_31[CLR28]...
Page 130 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name 1368h Ethernet Transmit frame interrupt EIR[TXF] 136Ch Ethernet Receive frame interrupt EIR[RXF] EIR[HBERR] EIR[BABR] EIR[BABT] EIR[GRA] EIR[TXB] 1370h Ethernet combined interrupt EIR[RXB] EIR[MII] EIR[EBERR] EIR[LC] EIR[RL] EIR[UN] 1388h PIT0 Channel 0 PIT_0_TFLG0[TIF]...
Page 131 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name DSPI_0 combined DSI and SPI Parity Error 1428h DSPI_0_SR[SPEF] Flags DSPI_4 combined overrun interrupt requests: 149Ch – FIFO underflow DSPI_4_SR[TFUF] | DSPI_4_SR[RFOF] – Receive FIFO overflow 14A0h DSPI_4 transmit FIFO end-of-queue flag DSPI_4_SR[EOQF] 14A4h DSPI_4 Tx FIFO fill request flag...
Page 132 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name LINFlexD_1 Transmission combined interrupt: LINFlexD_1_LINIER[HRIE] | – Header Received 15F4h LINFlexD_1_LINIER[DTIE] | – Data Transmitted LINFlexD_1_LINIER[DBEIE] – Data Buffer Empty LINFlexD_1 Error combined interrupt: – Stuck at zero LINFlexD_1_LINIER[SZIE] | LINFlexD_1_LINIER[OCIE] | –...
Page 133 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name SAR ADC0 combined interrupt: SARADC_0_ICIPR0[EOC_CH[7]] | SARADC_0_ICIPR0[EOC_CH[6]] | – NEOC (end of normal conversion of each SARADC_0_ICIPR0[EOC_CH[5]] | channel) SARADC_0_ICIPR0[EOC_CH[4]] I – NECH (end of normal chain) SARADC_0_ICIPR0[EOC_CH[8]] I 1840h –...
Page 134 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name SENT_0 Error combined interrupt: OR of following events: – Fast message DMA underflow – Slow message DMA underflow – Channels 0 to 3: - Successive calibration check resynchronized error SENT_0_GBL_STATUS[FMDU] | - Calibration variation 20 –...
Page 135 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name SENT_0 Channel 1 combined Error interrupt: – Successive calibration check resynchronized error – Calibration variation 20 – 25% – Slow message overflow – Fast message overflow SENT_0_CH1_STATUS[4:7] | 18E4h –...
Page 136 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name SIPI combined Error Interrupt: SIPI_ERR[TOEn] | SIPI_ERR[TIDEn] | – Channels 0 to 3 Timeout error 1A38h SIPI_ERR[ACKEn] – Channels 0 to 3 transaction ID error n = [0..3] –...
Page 137 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name LFAST_0 Receive Error combined interrupt: – Unsolicited frame register overflow LFAST_0_RISR[RXUOF] | LFAST_0_RISR[RXMNF] | – Rx Data FIFO Minimum Threshold reached LFAST_0_RISR[RXMXF] | – Rx Data FIFO Max Threshold reached LFAST_0_RISR[RXUFF] | 1A60h –...
Page 138 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name (M_CAN_2_IR[0] & ~M_CAN_2_ILS[0])| ... | (M_CAN_2_IR[11] & ~M_CAN_2_ILS[11]) | 1AC8h M_CAN_2 Line0 combined interrupt (M_CAN_2_IR[13] & ~M_CAN_2_ILS[13]) | … | (M_CAN_2_IR[31] & ~M_CAN_2_ILS[31]) (M_CAN_2_IR[0] & M_CAN_2_ILS[0])| ... | (M_CAN_2_IR[11] &...
Page 139 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name 1B60h DPLL_MSI: DPLL Missing STATE interrupt GTM_DPLL_IRQ[6] 1B64h DPLL_MTI: DPLL Missing TRIGGER interrupt GTM_DPLL_IRQ[7] 1B68h DPLL_SASI: DPLL STATE active slope detected GTM_DPLL_IRQ[8] DPLL_TASI: DPLL TRIG. active slope det. while 1B6Ch GTM_DPLL_IRQ[9] NTI_CNT is 0...
Page 140 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name GTM TIM0 Channel 1 shared interrupt: – New measurement value detected by SMU for channel (NEWVALx_IRQ) – ECNT counter overflow of channel (ECNTOFLx_IRQ) 1BB8h GTM_ICM_IRQG_2[TIM0_CH1_IRQ] – SMU counter overflow (CNTOFLx_IRQ) –...
Page 141 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name GTM TIM0 Channel 6 shared interrupt: – New measurement value detected by SMU for channel (NEWVALx_IRQ) – ECNT counter overflow of channel (ECNTOFLx_IRQ) 1BCCh GTM_ICM_IRQG_2[TIM0_CH6_IRQ] – SMU counter overflow (CNTOFLx_IRQ) –...
Page 142 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name GTM TIM1 Channel 3 shared interrupt: – New measurement value detected by SMU for channel (NEWVALx_IRQ) ECNT – Counter overflow of channel (ECNTOFLx_IRQ) 1BE0h GTM_ICM_IRQG_2[TIM1_CH3_IRQ] – SMU counter overflow (CNTOFLx_IRQ) –...
Page 143 RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name 1C34h GTM MCS0 Channel 0 interrupt GTM_ICM_IRQG_4[MCS0_CH0_IRQ] 1C38h GTM MCS0 Channel 1 interrupt GTM_ICM_IRQG_4[MCS0_CH1_IRQ] 1C3Ch GTM MCS0 Channel 2 interrupt GTM_ICM_IRQG_4[MCS0_CH2_IRQ] 1C40h GTM MCS0 Channel 3 interrupt GTM_ICM_IRQG_4[MCS0_CH3_IRQ] 1C44h GTM MCS0 Channel 4 interrupt GTM_ICM_IRQG_4[MCS0_CH4_IRQ]...
Page 144 Device configuration RM0400 Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name GTM TOM0 Event 7 combined interrupt: GTM_ICM_IRQG_9[TOM0_CH14_IRQ] | 1CD0h – TOM0 channel 14 event GTM_ICM_IRQG_9[TOM0_CH15_IRQ] – TOM0 channel 15 event GTM TOM1 Event 0 combined interrupt: GTM_ICM_IRQG_9[TOM1_CH0_IRQ] | 1CD4h –...
Page 145: Table 23. Latency Time Categories
RM0400 Device configuration Table 22. Interrupt sources(Continued) IRQ # Offset Source description Source name GTM_ERR_IRQ gtm_err_irq Decimation filter input buffer interrupt request 1E90 DECI_FILTR[IBIF] flag Decimation filter output buffer interrupt request 1E94 DECI_FILTR[OBIF] flag DECI_FILTR[DIVR] DECI_FILTR[OVF] DECI_FILTR[OVR] DECI_FILTR[IVR] 1E98 Decimation filter error interrupt request flag DECI_FILTR[SVR] DECI_FILTR[SCE] DECI_FILTR[SSE] 1E9C Clock Calibration on CAN event...
Page 146: Dma Controller Configuration
Device configuration RM0400 Figure 10. Interrupt timing Key for CPU Pipeline Stages Key for CPU Pipeline Stages Instruction Fetch Instruction Fetch D/EA D/EA Decode/Effective address calculation Decode/Effective address calculation Execute/Memory Access Execute/Memory Access Wait state Wait state Stall Stall Writeback Writeback IRQ signalled to IRQ signalled to...
Page 147: Dmachmux Configuration
RM0400 Device configuration Table 24. Reference links to related information Topic Related module Reference Chapter 19: Enhanced Direct Memory Access Full description DMA controller (eDMA) System memory map — Chapter 5: Memory map Register access Peripheral bridge Chapter 15: Peripheral Bridge Clocking —...
Page 148: Table 26. Dmamux Peripheral Dma Request To Input Source Mapping
Device configuration RM0400 6.3.8.3 DMA request mapping The mapping of the peripheral DMA requests to the DMA_CH_MUX input sources is shown Table Table 26. DMAMUX peripheral DMA request to input source mapping Peripheral DMA requests Source DMAMUX_0 DMAMUX_1 Reserved Reserved ADC_SAR_0 EOC Reserved Reserved...
Page 149 RM0400 Device configuration Table 26. DMAMUX peripheral DMA request to input source mapping(Continued) Peripheral DMA requests Source DMAMUX_0 DMAMUX_1 Reserved GTM_TOM0_IRQ5 Reserved GTM_TOM0_IRQ6 Reserved GTM_TOM0_IRQ7 Reserved GTM_ATOM0_IRQ0 Reserved GTM_ATOM0_IRQ1 Reserved GTM_ATOM0_IRQ2 Reserved GTM_ATOM0_IRQ3 Reserved GTM_MCS0_IRQ0 Reserved GTM_MCS0_IRQ1 Reserved GTM_MCS0_IRQ2 Reserved GTM_MCS0_IRQ3 Reserved GTM_MCS0_IRQ4...
Page 150: Memories And Memory Interfaces
Device configuration RM0400 Table 26. DMAMUX peripheral DMA request to input source mapping(Continued) Peripheral DMA requests Source DMAMUX_0 DMAMUX_1 Reserved Always on Always on Reserved Note: Just as multiple CHCONFIG registers within the same instance must not select the same source value, CHCONFIG registers among multiple instances must not select the same source value.
Page 151: Flash Memory Controller (Pflash) Configuration
RM0400 Device configuration Table 29. Reference links to related information Topic Reference Embedded memories Chapter 3: Embedded memories System memory map Chapter 5: Memory map Platform Flash Chapter 28: Flash memory controller (PFLASH Controller) Platform RAM Controller Chapter 27: RAM controller (PRAM) Embedded flash memory Chapter 28: Flash memory controller (PFLASH Controller) Decorated Storage Memory Controller...
Page 152: Decorated Storage Memory Controller (Dsmc)
Device configuration RM0400 Table 30. Flash controller bus master assignments(Continued) Bus master number Bus master Reserved Reserved Table 31. Reference links to related information Topic Related module Reference Chapter 28: Flash memory controller Full description Flash Memory Controller (PFLASH) (PFLASH Controller) Flash memory architecture Flash memory, Flash controller Section 3.3: Embedded flash memory...
Page 153: Ecc Error Reporting Module
RM0400 Device configuration 6.4.3 ECC Error Reporting Module The Error Reporting Module (ERM) provides information and optional interrupt notification on memory error events associated with ECC (Error Correction Code). The ERM collects ECC events on memory accesses for local memory arrays, such as flash, system RAM or peripheral RAMs.
Page 154: Analog Modules
Device configuration RM0400 6.4.5 Analog modules This section highlights the following analog modules that are implemented on SPC572Lx: Table 34. Analog modules Module or Subsystem Device-specific information Block details Section 6.4.6: Temperature sensor Temperature sensor Chapter 38: Temperature Sensor configuration ADC subsystem Section 34.1: ADC overview See individual modules...
Page 155: Sdadc Configuration
RM0400 Device configuration 6.4.8 SDADC configuration The Sigma-Delta Analog-to-Digital Converter (SDADC) digital interface block controls the on-chip SDADC and holds control and status registers accessible for application. It provides the accurate conversion data for a wide range of applications. SPC572Lx includes one independent 16-bit SDADC. For details, see Chapter 34: Analog-to-digital converter (ADC) configuration.
Page 156: System Timer Module (Stm) Configuration
Device configuration RM0400 The GTM101 is an implementation of the Robert Bosch GmbH GTM timer subsystem. It is not a single module, but a complex timer subsystem that consists of many modules that can be used to implement highly complex timer functions. System Timer Module (STM) configuration The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions.
Page 157: Pit Configuration
RM0400 Device configuration Table 37. SWT register reset values SWT instance Register Reset value SWT0 SWT Control Register (SWT_CR) 0xFF00_010A SWT0 SWT Time-out (SWT_TO) 0x0005_FCD0 SWT2 SWT Control Register (SWT_CR) 0xFF00_011B SWT2 SWT Time-out (SWT_TO) 0x0003_FDE0 SWT3 SWT Control Register (SWT_CR) 0xFF00_010A SWT3 SWT Time-out (SWT_TO)
Page 158: Table 38. Reference Links To Related Information
Device configuration RM0400 Figure 13. PIT configuration Peripheral bridge Register access Periodic interrupt timer Table 38. Reference links to related information Topic Related module Reference Full description Chapter 41: Periodic Interrupt Timer (PIT) System memory map — Chapter 5: Memory map Clocking —...
Page 159: Gtm Integration Module Configuration
RM0400 Device configuration Table 40. PIT1 memory map Absolute address (hex) Register name FFF8_0000 PIT Module Control Register (PIT1_MCR) FFF8_00E0 – Reserved FFF8_00E4 FFF8_00F0 – Reserved FFF8_00FC Timer Channel [0:3] Registers (PIT1_LDVALn, PIT1_CVALn, PIT1_TCTRLn, and FFF8_0100 – FFF8_017C PIT1_TFLGn) FFF8_0180 – FFF8_3FFF Reserved 1.
Page 160: Can Nodes
Device configuration RM0400 The MII Management Frame Register (MMFR) is not supported on SPC572Lx. Note: The RMII_MODE field is fixed by hardware to ‘1’, and is not configurable by the user. Refer to Chapter 48: Fast Ethernet Controller (FEC) for detailed description. 6.7.2 CAN nodes Table 42...
Page 161: Table 43. Reference Text To Related Information
RM0400 Device configuration Figure 14. LFAST and SIPI block diagram Config Config SIPI Initiator LFAST LFAST external Master interface slave SIPI Target 6.7.3.2 Device specific features The LFAST can operate in either slave or master mode configurations. The node running in master mode controls the serial link but SIPI in both master and slave nodes can act as both Initiator and Target for SIPI commands simultaneously.
Page 162: Dspi Configuration
Device configuration RM0400 Table 43. Reference text to related information(Continued) Topic Related Module Reference Chapter 19: Enhanced Direct Memory Access Direct Memory Access eDMA (eDMA) System Memory Map — Chapter 5: Memory map 6.7.4 DSPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 163: Table 45. Dspi Instantiation
RM0400 Device configuration Table 45. DSPI instantiation Data TX FIFO RX FIFO DSPI module CTARs PCS signals LVDS support serialization depth depth support DSPI0 PCS[7:0] Not available — DSPI4 PCS[7:0] Available 1. Supports Microsecond Bus SCK and SOUT LVDS signal pairs. 6.7.4.2 Serial input for DSI mode Serial input for the DSI mode is selected using the SIUL register...
Page 164: Table 46. Dspi Registers Memory Map
Device configuration RM0400 6.7.4.7 DSPI ITSB Mode For the ITSB trigger, the internal DSPI trigger (TRGPRD in DSICR1) will be used. Use of external trigger is not supported. 6.7.4.8 DSPI registers Table 46 shows the absolute addresses of DSPI module registers in this MCU. Table 46.
Page 165 RM0400 Device configuration Table 47. DSPIx_MCR field descriptions(Continued) Field Description DSPI Configuration Selects among the different configurations of the DSPI. 2–3 00 SPI DCONF 01 DSI 10 CSI 11 Reserved Freeze Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug mode.
Page 166 Device configuration RM0400 Table 47. DSPIx_MCR field descriptions(Continued) Field Description Disable Receive FIFO When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double- buffered SPI. This bit can only be written when the MDIS bit is cleared. DIS_RXF 0 Rx FIFO is enabled.
Page 167: Sent Receiver (Srx) Configuration
RM0400 Device configuration Table 47. DSPIx_MCR field descriptions(Continued) Field Description Parity Error Stop Controls SPI operation when a parity error is detected in a received SPI frame. 0 SPI frame transmission continues. 1 SPI frame transmission stops. Halt Starts and stops DSPI transfers. HALT 0 Start transfers.
Page 168 Device configuration RM0400 Table 48. SENT receiver memory map(Continued) Offset Register name SENT 0 0x0048 DMA_FMSG_TS—DMA Fast Message Time Stamp Read Register 0x004C Reserved — 0x0050 DMA_SMSG_BIT3—DMA Serial Message Read Register (Bit 3) 0x0054 DMA_SMSG_BIT2—DMA Serial Message Read Register (Bit 2) 0x0058 DMA_SMSG_TS—DMA Serial Message Time Stamp Read Register 0x005C...
Page 169: Linflexd - Configurations
RM0400 Device configuration Table 48. SENT receiver memory map(Continued) Offset Register name SENT 0 0x0194 CH2_FMSG_CRC—Channel ‘n’ Fast Message CRC Register 0x0198 CH2_FMSG_TS—Channel ‘n’ Fast Message Time Stamp Register 0x019C CH2_SMSG_BIT3—Channel ‘n’ Serial Message Register (Bit 3) 0x01A0 CH2_SMSG_BIT2—Channel ‘n’ Serial Message Register (Bit 2) 0x01A4 CH2_SMSG_TS—Channel ‘n’...
Page 170 Device configuration RM0400 Table 50. LINFlexD implemented registers(Continued) linflex_0 linflex_1 linflex_14 0xFFE8C000 0xFFE90000 0xFFEA8000 Register description Address offset Address offset Address offset (hex) (hex) (hex) LIN Error Status register (LINESR) UART Mode Control register (UARTCR) UART Mode Status register (UARTSR) LIN Timeout Control Status register (LINTCSR) LIN Output Compare register (LINOCR) LIN Timeout Control register (LINTOCR)
Page 171: Reset And Boot Modules
RM0400 Device configuration Table 50. LINFlexD implemented registers(Continued) linflex_0 linflex_1 linflex_14 0xFFE8C000 0xFFE90000 0xFFEA8000 Register description Address offset Address offset Address offset (hex) (hex) (hex) UART Preset Timeout register (UARTPTO) UART Current Timeout register (UARTCTO) DMA Tx Enable register (DMATXE) DMA Rx Enable register (DMARXE) 6.7.8 Reset and Boot modules...
Page 172: Table 53. Boot Header Structure
Device configuration RM0400 The first header found that contains the value 005Ah in the first half-word is valid for booting. The whole header structure is shown in Table Table 53. Boot header structure Address offset Contents Boot Header Configuration (see Figure Boot Core Reset Vector Reserved...
Page 173: System Status And Configuration Module (Sscm) Configuration
RM0400 Device configuration 6.7.10 System Status and Configuration Module (SSCM) configuration This section summarizes the System Status and Configuration Module (SSCM) configuration in the SPC572Lx. For a comprehensive description of the SSCM, please refer to the SSCM’s dedicated chapter. 6.7.10.1 SSCM instantiation There is one SSCM instance in the SPC572Lx device.
Page 174: Table 57. Protected Siul2 Registers
Device configuration RM0400 Table 56. Reference links to related information(Continued) Topic Related module Reference CMU registers CMU, CMUIOP Chapter 23: Clock Monitor Unit (CMU) PMC Digital Interface Chapter 54: Power Management Controller digital PMC_DIG (PMC_DIG) registers interface (PMC_dig) PLL Digital Interface PLLDIG Chapter 22: PLL Digital Interface (PLLDIG) (PLL_DIG) registers...
Page 175: Table 58. Protected Cmuiop Registers
RM0400 Device configuration Table 57. Protected SIUL2 registers(Continued) Offset from module Register Register size (bits) Protected size (bits) base address MCSR 612 — MCSR 624 — MCSR 628 — MCSR 638-639 — MCSR 643 — MCSR 656-687 — 32 (×22) MCSR 758 —...
Page 176: Table 60. Protected Plldig Registers
Device configuration RM0400 Table 59. Protected PMC_dig registers(Continued) Offset from module Register Register size (bits) Protected size (bits) base address RES_VD7 0x0078 REE_VD9 0x0094 RES_VD9 0x098 REE_VD10 0x0A4 RES_VD10 0x0A8 REE_TD 0x0304 RES_TD 0x0308 CTL_TD 0x030C MREG_CTRL 0x240 VD_UTST 0x340 ADC_CH 0x344 6.7.12.4...
Page 177: Table 62. Protected Mc_Me Registers
RM0400 Device configuration Table 62. Protected MC_ME registers Offset from module Register Register size (bits) Protected size (bits) base address ME_MCTL 0x0004 ME_ME 0x008 ME_IM 0x010 ME_SAFE_MC 0x028 ME_DRUN_MC 0x02C ME_RUN0_MC 0x030 ME_RUN1_MC 0x034 ME_RUN2_MC 0x038 ME_RUN3_MC 0x03C ME_RUN_PC0-7 0x080 – 0x09C ME_PCTL 0 –...
Page 178: Security Modules
Device configuration RM0400 Table 64. Protected MC_RGM registers(Continued) Offset from module Register Register size (bits) Protected size (bits) base address RGM_FESS 0x340 RGM_PRST0–7 0x610–62C 6.7.12.9 System Status and Control Module (SSCM) protected registers Table 65 lists the SSCM registers that can be protected. Table 65.
Page 179: Figure 18. Pass_Lock0_Pgn Register
Figure 18. PASS_LOCK0_PGn register Bit number Register field LOWLOCK[13:0] MIDLOCK[15:0] Flash block — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — name Read lock —...
Page 180: Figure 20. Pass_Lock2_Pgn Register
Figure 19. PASS_LOCK1_PGn register Bit number Flash block — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — name Read Read lock Lock —...
Page 181: Figure 21. Pass_Lock3_Pgn Register
Figure 21. PASS_LOCK3_PGn register Bit number Register bit MSTR Reserved 256KLOCK[15:0] name Flash block — Master Access — — — — — — — — — — — — — — — — — — — — — name...
Page 182: Table 67. Pass Dcf Records
Device configuration RM0400 6.8.1.2 PASS Module DCF Records (includes life cycle state and censorship) The records required to configure the initial values for the PASS module password group registers is shown in Table 67. These values provide the following capabilities: •...
Page 183: Debug And Calibration Architecture
RM0400 Device configuration Table 67. PASS DCF records(Continued) DCF address (binary) Number of DCF CS[14:0] DCF client description [16:10] [9:2] Valid bits DCF records 000_0000_0000_1000 0000000 01001111 LOCK3_PG3 01001100– 000_0000_0000_1000 0000000 Reserved 11111111 1. See Section 68.5.4: Censoring and uncensoring the device for values 2.
Page 184: Figure 22. Debug And Calibration Architecture For Spc572Lx
Device configuration RM0400 Figure 22. Debug and calibration architecture for SPC572Lx 184/2058 DocID027809 Rev 4...
Page 185: Reset And Boot
RM0400 Reset and Boot Reset and Boot Introduction Resetting the SPC572Lx involves an entire process starting with the application of power to fetching the first instruction of the user’s application code. The processor core on the SPC572Lx is based on the e200z215An3 architecture. Memory elements involved in the boot-up process include: •...
Page 186: Boot Header
Reset and Boot RM0400 7.1.4 Boot header A boot header is used to supply the start address for code execution for the Core. It is written by the application programmer and loaded into specific locations in flash memory. The boot header contains the reset vectors for the core. Modules used in reset sequence The modules involved in the SPC572Lx reset sequence are: •...
Page 187: Mode Entry Module
RM0400 Reset and Boot normally and the state of analog modules, specific digital modules (e.g., debug and flash memory modules) and system memory content is preserved. Examples of functional resets are: • External reset. • Machine check. • Software reset from mode entry. •...
Page 188: Power-On And The Reset Generation Module
Reset and Boot RM0400 7.3.1 Power-on and the Reset Generation Module When power is applied to the SPC572Lx, the Reset Generation Module (MC_RGM) advances the device through a series of steps shown in Figure The Reset Generation Module (MC_RGM) starts the System Status and Control Module (SSCM), which continues the boot-up process detailed in Figure 24 through to...
Page 189: Power-Up Phase: Power Stabilization
RM0400 Reset and Boot Table 68. Module status during reset phases PHASE Module PHASE0 PHASE1 PHASE2 PHASE3 IDLE IRCOSC MC_RGM System watchdog RESET RESET RESET Flash module RESET RESET XOSC RESET DEVICE CONFIG RESET HOLD HOLD HOLD HOLD SSCM RESET RESET RESET Core...
Page 190: Phase0 Phase: Analog Supply Initial Configuration
Reset and Boot RM0400 managed by the PMC, which provides enable and status bits for these voltage detection circuits. The PMC sends a signal to the Reset Generation Module when power stabilization has been achieved. The Reset Generation Module then advances to the PHASE0 state (see Figure 23).
Page 191: Phase1: Temporization And Monitoring Setup
RM0400 Reset and Boot To exit PHASE0 and enter PHASE1: • All enabled destructive resets must be processed. • Gating PHASE0 must be released. See Table 74: POR and voltage monitors description. • All processes initiated in PHASE0 must be completed. This generally includes startup of the internal analog modules: PMC, IRCOSC, and I/Os.
Page 192: Idle Phase
Reset and Boot RM0400 During PHASE3, the System Status and Configuration Module (SSCM) starts by retrieving the Device Configuration Format (DCF) record from the TEST and UTEST flash memory areas, and uses the configuration and initialization information therein to: • Configure the initial memory map of the device.
Page 193: Mc_Rgm Passes Boot Sequence Control To The System Status And Control
RM0400 Reset and Boot MC_RGM passes boot sequence control to the System Status and Control Module A flow chart of the boot-up sequence is shown in Figure Figure Figure 26, and Figure 7.4.1 Reset sequence flow based on initial device condition The boot-up sequence takes different paths depending on which modules are enabled and which header files are present.
Page 194 Reset and Boot RM0400 7.4.3.1 Assumptions • Boot Assist Flash bypass mode is not enabled (execute BAF code). • Application code for the Boot CPU is programmed into flash memory. • A valid boot header has been programmed into flash memory. –...
Page 195 RM0400 Reset and Boot 7.4.3.6 BAF code execution begins (state 22) After the reset signal is released to the core, BAF code execution begins. 7.4.3.7 The Core executes code to apply device setting (state 23) The core executes BAF code written by the manufacturer to apply specific device settings to the SPC572Lx.
Page 196: Path From Mc_Rgm Idle To Serial Boot Mode
Reset and Boot RM0400 7.4.4 Path from MC_RGM IDLE to serial boot mode Here no application program or valid boot header is programmed into flash memory. It is an unusual scenario, but it is shown here for illustrative purposes. 7.4.4.1 Initial conditions •...
Page 197 RM0400 Reset and Boot The SSCM releases reset to the core and then turns on the clock to the core. The start address is transferred to the core at this time under the control of the SSCM and the core begins execution of the BAF code.
Page 198: Path From Mc_Rgm Idle With Core Enabled To Watchdog Timer Timeout
Reset and Boot RM0400 7.4.4.11 Enter serial boot mode (state 14) Figure 27: Boot-up sequence, part D shows the boot loader flow. 7.4.4.12 Life Cycle check indicates FACTORY (decision point G) There are two possible settings for the Life Cycle parameter: •...
Page 199 RM0400 Reset and Boot 7.4.5.2 Reset Generation Module has entered idle state (state 1 and 2) Once the IDLE phase is signaled, the System Status and Control Module (started in PHASE3) continues with the system boot-up sequence while the MC_RGM waits for new events that trigger a reset sequence.
Page 200 Reset and Boot RM0400 This is the header file for the CPU that starts executing the user application code. The Boot CPU header is programmed into flash memory at the same time the user application program is programmed into flash memory. The core searches for the boot header, which can be located at one of four addresses: •...
Page 201: Figure 24. Boot-Up Sequence Part A
RM0400 Reset and Boot Figure 24. Boot-up sequence part A LOGIC / SSCM Configuration data is read from OTP UTEST flash during reset BIST configuration phase3 This is checked during Trim & option bits inc. WD reset phase3 Flash BAF present Default JTAG test...
Page 202: Figure 25. Boot-Up Sequence Part B
Reset and Boot RM0400 Figure 25. Boot-up sequence part B OTP flash BAF Execute Flash BAF Apply device settings Search and parse boot header Valid Boot Header? Decode boot CPU Initialize RAM Lock BAF instruction access Boot from internal Flash Serial Boot Mode 202/2058 DocID027809 Rev 4...
Page 203: Figure 26. Boot-Up Sequence, Part C
RM0400 Reset and Boot Figure 26. Boot-up sequence, part C SSCM BAF bypass mode Search and parse boot header Valid Lock BAF boot ID? instruction access Provide application Provide flash BAF code start address to serial boot code reset Core, negate ERS0 & vector to Core, negate Core clock gate ESR0 &...
Page 204: Figure 27. Boot-Up Sequence, Part D
Reset and Boot RM0400 Figure 27. Boot-up sequence, part D Serial boot mode field Life cycle check? Stop (wait for watchdog) factory Configure LINFlexD & pins Wait for START WORD Receive valid START WORD Receive START ADDRESS Receive DOWNLOAD SIZE Receive CODE Branch to start address Serial boot process flow diagram...
Page 205: Device Configuration Format (Dcf) Records
RM0400 Device Configuration Format (DCF) Records Device Configuration Format (DCF) Records Introduction Device Configuration Format (DCF) records are used to configure certain registers in the device during system boot while the reset signal is asserted. An individual DCF record consists of a pointer to the location of a register internal to the device and the respective data.
Page 206: Dcf Records
Device Configuration Format (DCF) Records RM0400 ‘TEST DCF Record Only’ so that only DCF Records stored in TEST flash can write to the DCF Client. A list of DCF clients is shown in Table 71. (TEST DCF Record Only clients are not shown as these are not accessible by the user).
Page 207: Figure 29. Dcf Start Record
RM0400 Device Configuration Format (DCF) Records Table 69. DCF record field description(Continued) Field Description Parity Bit for the DCF Record. Parity Note: This bit is NOT implemented for DCF Clients written from UTEST. This bit indicates the end of the list of DCF Records. Note: The Erased state of flash is 0xFFFF_FFFF_FFFF_FFFF.
Page 208: Table 70. Series Of Dcf Records In Utest Flash Memory
Device Configuration Format (DCF) Records RM0400 The general format of the stop record is shown in Figure 30. Only the stop bit needs to be ‘1’ in order to form a stop record—all other bits are ignored. An unprogrammed location in UTEST flash is interpreted as a stop record.
Page 209: Utest Dcf Records
RM0400 Device Configuration Format (DCF) Records Figure 31. Appending DCF records No Start Record Start Record Start Record No Start Record Data Record - CS1, Ad = 0 Data Record - CS1, Ad = 0 No Start Record Data Record - CS2, Ad = 0 Data Record - CS2, Ad = 0 No Start Record Data Record - CS0, Ad = 0...
Page 210: Dcf Client List
Device Configuration Format (DCF) Records RM0400 include different write strategies listed below. The following list defines the special strategies: – None—no special DCF strategy is used. – Parity—not implemented for UTEST DCF clients. Used for TEST Only DCF clients not accessible to the user. –...
Page 211 RM0400 Device Configuration Format (DCF) Records Table 71. DCF client list (Continued) Estimat Reset Typical client order UTEST DCF address IPS read DCF client value of value of specia dependen flash DCF CS[14:0] [16:2] direct description memor (binary) access client client strateg in flash...
Page 212 Device Configuration Format (DCF) Records RM0400 Table 71. DCF client list (Continued) Estimat Reset Typical client order UTEST DCF address IPS read DCF client value of value of specia dependen flash DCF CS[14:0] [16:2] direct description memor (binary) access client client strateg in flash...
Page 213 RM0400 Device Configuration Format (DCF) Records Table 71. DCF client list (Continued) Estimat Reset Typical client order UTEST DCF address IPS read DCF client value of value of specia dependen flash DCF CS[14:0] [16:2] direct description memor (binary) access client client strateg in flash...
Page 214 Device Configuration Format (DCF) Records RM0400 Table 71. DCF client list (Continued) Estimat Reset Typical client order UTEST DCF address IPS read DCF client value of value of specia dependen flash DCF CS[14:0] [16:2] direct description memor (binary) access client client strateg in flash...
Page 215 RM0400 Device Configuration Format (DCF) Records Table 71. DCF client list (Continued) Estimat Reset Typical client order UTEST DCF address IPS read DCF client value of value of specia dependen flash DCF CS[14:0] [16:2] direct description memor (binary) access client client strateg in flash...
Page 216: Miscellaneous Dcf Registers
Device Configuration Format (DCF) Records RM0400 8.4.2 Miscellaneous DCF registers Offset: 000000000000000 Access: DCF Client The reset value is chip-specific; see the chapter that describes how modules are configured and Reset connected. XOSC LOAD CAP SEL[4:0] The reset value is chip-specific; see the chapter that describes how modules are configured and Reset connected.
Page 217 RM0400 Device Configuration Format (DCF) Records Table 72. UTEST Miscellaneous DCF Client field descriptions(Continued) Field Description XOSC ALC_DIS 0 Enable Automatic Level Controller XOSC ALC_DIS 1 Disable Automatic Level Controller XOSC LF_EN 0 Oscillator is not used for low frequency (~8 MHz) 1 Oscillator is used for low frequency (~8 MHz) XOSC LF_EN It is possible to use a low-frequency oscillator (<...
Page 218: Power Management
Power management RM0400 Power management Overview SPC572Lx microcontrollers include a robust power management infrastructure for applications to select various Operational and Low-power modes and monitor internal voltages for High- and Low-voltage conditions. This monitoring is also used to ensure supply voltages and internal voltages are within the required ranges before the microcontroller leaves reset.
Page 219: Power Management Supply Description
RM0400 Power management Figure 33. Device power management framework Notes: LV = Low Voltage (1.2 V) HV = High Voltage (5.0 V) PD = Power Domain PCU = Power Control Unit RGM = Reset Generation Module CGM = Clock Generation Module CGL = Clock Gating Logic ME = Mode Entry unit Flash...
Page 220: Spc572Lx Power Management Controller Overview
Power management RM0400 9.1.3 SPC572Lx power management controller overview SPC572Lx power management controller (PMC) implements the following modules: • Main regulator with internal ballast with dedicated reference. • LVDs monitoring low voltage supply with characteristics as defined in Table 74 working on dedicated reference, different from regulator reference.
Page 221: Figure 35. Device High Voltage Power-Ground Network
RM0400 Power management Main regulator uses dedicated reference supplied by VDD_HV_PMC. 9.1.3.2 SPC572Lx power management controller integration The power management controller has two separate supplies: • VDD_HV_PMC: provides the main module supply to the power management controller • VDD_HV_IO_MAIN: provides the low voltage ballast supply. Note: The internal ballasts are distributed around the device to reduce the temperature gradient on the silicon.
Page 222: Low Power Mode Support
Power management RM0400 Figure 36. Device low voltage power-ground network Low Voltage VDD_LV_CORE VDD_LV_PLL0 VDD_LV_FLA Power / Ground network VSS_LV VSS_LV_PLL0 VSS_LV_FLA pin101/81 pin 52/42 FLASH pin101/81 pin 52/42 pin 52/42 pin101/81 pin101/81 pin 52/42 pin 52/42 pin101/81 pin101/81 pin 52/42 PLL0 pin 52/42 pin101/81...
Page 223: Low Power Support And Stop Mode Implementation
RM0400 Power management 9.2.1 Low power support and STOP mode implementation Low power mode may be used to control the engine during the power-up phase, as in a Start-Stop system or when the key has been turned off. After-run is defined as part of RFQ500, the requirement has since been clarified as follows. The device implements the equivalent of an idle or power-down mode through STOP and HALT mode configuration.
Page 224: Flash Power Requirements
Power management RM0400 Device implements all three mechanisms to exit from stop mode: pin wakeup, CAN wake-up and timed wake-up. Some customer implementations may use an external ASIC regulator that does not have low-power mode support. The Asic regulator is either on or off, with no possibility of changing the regulated output in operation.
Page 225: Device Trimming
RM0400 Power management Device trimming During the initialization phase, the device defaults to a pre-determined state for each of the LVDs. As the flash becomes available, the differential read process allows the trimming data to be available for the internal LVDs. Refer to <Cross Refs>Section 9.6, Power sequence for further details.
Page 226: Low Voltage Detection (Lvd)
Power management RM0400 Figure 37. Internal LVD and HVD in configuration example during power-up DEVICE EXTERNAL System kept Device Initialization Operating mode Out of SoC REGULATOR under Reset specification (Example) +11% 1.388V 1.338V VDD_LV 1.275V core Static (MCU) 1.250V regulator 1.225V 1.200V 1.200V...
Page 227: Table 74. Por And Voltage Monitors Description
RM0400 Power management Note: LVD098 and LVD270 (low range LVDs) cannot be disabled by the user during boot sequence. These modules are used during the power-up phase and ensure that the absolute lowest threshold of operation is not breached. This is not a guarantee that the device will function down to this level, only that the device will recover if this level is crossed.
Page 228: Table 75. Voltage Monitors Configurability
Power management RM0400 1. REE: Reset event enable. IE: Interrupt enable — See Chapter 54: Power Management Controller digital interface (PMC_dig). Table 75 provides the monitor status depending on configuration. Table 75. Voltage monitors configurability POWER PHASE Monitor status 0-1-2 Default configuration (boot threshold monitor) ENABLE ENABLE —...
Page 229: Power Sequence
RM0400 Power management Table 75. Voltage monitors configurability(Continued) POWER PHASE Monitor status 0-1-2 – Monitor enabled in PHASE 3 on DCF record reading. DISABLE DISABLE ENABLE ENABLE DEST — – Trigger reset event. – Configuration locked to enable during run time.
Page 230: Power-Up Sequence
Power management RM0400 An internal power-on signal identifies the POWERUP state when the device is not supplied or partially supplied, and is released high on power-sequence exit. The signal is a combination of LVDs monitoring: • VDD_LV • VDD_HV_PMC • VDD_HV_IO •...
Page 231 RM0400 Power management 2. POWERUP state is maintained until supply cross the power-on reset threshold: V for LV supply, V PORUP_LV PORUP_HV high voltage supply. 3. Before software configuration 4. ESR0 configuration moves from strong pull-down to weak pull-up on completion of internal reset sequence (PHASE3[FUNC]).
Page 232: Figure 38. Example Of Vdd_Lv Power-Up Sequencing
Power management RM0400 Figure 38 provides an example of VDD_LV power-up sequence from POWERUP to PHASE3. Figure 38. Example of VDD_LV power-up sequencing POWERUP Power-ON Time LVD LVD Trimming Flash init stabilization Available (SSCM) start when enabled LVD108 disabled (used modules must work at LVD098) VDD_LV 1.140V LVD108_C...
Page 233: Figure 39. Threshold Variation During Power-Up Sequence
RM0400 Power management Figure 39. Threshold variation during power-up sequence POWERUP P0 P1 1.440 V 1.380 V +11% 1.320 V 1.275 V 1.250V 1.225 V 1.200 V –4% 1.180 V –9% 1.140 V 50 mV hysteresis +40 mV max internal drop Fully functional MAX THRESHOLD 1.080 V...
Page 234: Figure 40. Vdd_Hv Monitored Voltages During Power-Up
Power management RM0400 Figure 40. VDD_HV monitored voltages during power-up VDD_HV_IF VDD_HV_FLA VDD_HV_PMC pin LVD270_C LVD290_IF LVD290_F DEVICE VDD_HV_IM pin LVD400_IM VDD_HV_IJ pin LVD290_IJ VDD_HV_ADC LVD400_A After both LV and HV POWERUP exit conditions have been verified, ipp_por_en_b signal is released to all analog modules. The IRCOSC module starts initialization and provides the clock to the system after .
Page 235: Power-Down Sequence
RM0400 Power management Figure 41. Threshold variation during power-up sequence POWERUP P0 P1 6.0 V 5.5 V 4.5 V 3.9 V 3.6 V Fully functional Functional Margin 3.0 V 100 mV hysteresis UPPER THRESHOLD Reliability restriction LOWER THRESHOLD 2.7 V Out of spec The device needs to fulfill all conditions described on Section 9.6.1: Power-up sequence...
Page 236: Low Voltage Requirement During Crank
Power management RM0400 Warning: LVD270 monitors can be disabled for test purposes via software access of the PMC_REE register. However, the internal monitors of the device may not detect that VDD_HV voltage is outside functional range (below LVD270 threshold) so the user must ensure a reset state by assertion of the external PORST pin.
Page 237: Security
RM0400 Security Security This device has a comprehensive set of customer-configurable security features designed to protect code and data from unauthorized access. 10.1 Basic security All SPC572Lx devices have the following basic set of security features. • Device censorship based on the life cycle model with code and data access progressively more restricted as device matures through defined life cycle steps •...
Page 238: Calibration And Debug
Calibration and Debug RM0400 Calibration and Debug The chapter discusses the device specific information for the debug and calibration modules. The device starts up in JTAG mode. All standards used have freely available specifications for tool developers. The Event Out (EVTO[0,1]) signals are connected to the external TGOUT[0,1] device pins and the Event In (EVTI) signals are connected to the external TGIN[0,1] device pins.
Page 239: Debug And Calibration Interface (Dci)
RM0400 Calibration and Debug 11.2.1 Debug and Calibration Interface (DCI) The Debug and Calibration Interface (DCI) module provides debug and calibration features. The DCI module includes the device JTAG controller, the IEEE 1149.7 interface. The DCI provides the following features: •...
Page 240: Table 79. Dci_Pincr Register Field Descriptions
Calibration and Debug RM0400 11.2.1.1 DCI EVTx pin multiplexing control register (DCI_PINCR) The DCI EVTx pin multiplexing control register (DCI_PINCR) is described below. The EVTI and EVTO functions share the same set of possible pins. If this register is written to enable both EVTI and EVTO on the same pin, the EVTI function is selected, although this type of programming should be avoided.
Page 241: Jtag Data Communication (Jdc)
RM0400 Calibration and Debug Table 79. DCI_PINCR register field descriptions(Continued) Field Description Enables EVTI[0] function on pin PA[9] EVTI0B Enables EVTI[0] function on pin PA[8] EVTI0A 11.2.1.2 JTAG Controller (JTAGC) The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode.
Page 242: Table 80. L1Sel0 Register Field Descriptions
Calibration and Debug RM0400 Table 80. L1SEL0 register field descriptions Field Description 000 Reserved 001 Reserved 010 CPU instruction address compare 1 (watchpoint 0) 011 Reserved MUX 0 100 Reserved 101 Reserved 110 Reserved 111 Reserved 000 Reserved 001 Reserved 010 CPU instruction address compare 2 (watchpoint 1) 011 Reserved MUX 1...
Page 243: Table 81. L1Sel1 Register Field Descriptions
RM0400 Calibration and Debug Table 80. L1SEL0 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 CPU instruction address compare 7 (watchpoint 14) 011 Reserved MUX 6 100 Reserved 101 Reserved 110 CPU debug event input 2 (watchpoint 11) 111 CPU debug event output 3 (watchpoint 21) 000 Reserved 001 Reserved...
Page 244 Calibration and Debug RM0400 Table 81. L1SEL1 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 CPU instruction address compare 4 (watchpoint 3) 011 Reserved MUX 11 100 Reserved 101 Reserved 110 Reserved 111 Reserved 000 Reserved 001 Reserved 010 CPU instruction address compare 5 (watchpoint 8) 011 Reserved MUX 12...
Page 245: Table 82. L1Sel2 Register Field Descriptions
RM0400 Calibration and Debug Table 82. L1SEL2 register field descriptions Field Description 000 Reserved 001 Reserved 010 CPU data address compare 1 (watchpoint 4) 011 Reserved MUX16 100 Reserved 101 Reserved 110 Reserved 111 Reserved 000 Reserved 001 Reserved 010 CPU data address compare 2 (watchpoint 5) 011 Reserved MUX 17 100 Reserved...
Page 246: Table 83. L1Sel3 Register Field Descriptions
Calibration and Debug RM0400 Table 82. L1SEL2 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 CPU data address compare 3 (watchpoint 6) 011 Reserved MUX 22 100 Reserved 101 Reserved 110 Reserved 111 Reserved 000 Reserved 001 Reserved 010 CPU data address compare 4 (watchpoint 7) 011 Reserved MUX 23...
Page 247 RM0400 Calibration and Debug Table 83. L1SEL3 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 CPU data address compare 4 (watchpoint 7) 011 Reserved MUX 27 100 Reserved 101 Reserved 110 CPU write to BUCSR 111 Reserved 000 Reserved 001 Reserved 010 CPU data address compare 1 (watchpoint 4) 011 Reserved...
Page 248: Table 84. L1Sel4 Register Field Descriptions
Calibration and Debug RM0400 Table 84. L1SEL4 register field descriptions Field Description 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 32 100 Reserved 101 Reserved 110 Production device NAR full 111 GTM watchpoint 0 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 33 100 Reserved...
Page 249: Table 85. L1Sel5 Register Field Descriptions
RM0400 Calibration and Debug Table 84. L1SEL4 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 38 100 Reserved 101 Reserved 110 Reserved 111 GTM watchpoint 6 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 39 100 Reserved 101 Reserved...
Page 250 Calibration and Debug RM0400 Table 85. L1SEL5 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX43 100 Reserved 101 Reserved 110 SPU counter event 3 111 GTM watchpoint 11 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 44 100 Reserved...
Page 251: Table 86. L1Sel6 Register Field Descriptions
RM0400 Calibration and Debug Table 86. L1SEL6 register field descriptions Field Description 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 48 100 Reserved 101 Reserved 110 SPU counter event 8 111 Reserved 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 49 100 Reserved 101 Reserved...
Page 252: Table 87. L1Sel7 Register Field Descriptions
Calibration and Debug RM0400 Table 86. L1SEL6 register field descriptions(Continued) Field Description 000 CPU interrupt current priority match to C2PIS 001 CPU write to ME bits of MSR 010 Reserved 011 Reserved MUX 54 100 Reserved 101 Reserved 110 SPU counter event 14 111 Reserved 000 Reserved 001 Reserved...
Page 253: Calibration Interface
RM0400 Calibration and Debug Table 87. L1SEL7 register field descriptions(Continued) Field Description 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 59 100 Reserved 101 Reserved 110 Reserved 111 DCI EVTO1 000 Reserved 001 Reserved 010 Reserved 011 Reserved MUX 60 100 Reserved 101 Reserved 110 Reserved...
Page 254: Jtag Master (Jtagm)
Calibration and Debug RM0400 Table 88. Reference links to related information Related module Reference JTAG Master (JTAGM) Chapter 62: JTAG Master (JTAGM) Development Tool Semaphore (DTS) Chapter 64: Development Trigger Semaphore (DTS) 11.3.1 JTAG Master (JTAGM) The JTAG Master (JTAGM) is a module that is able to act as JTAG master inside the device. The module has a parallel interface that can exchange data via customer software.
Page 255: Nexus Aurora
RM0400 Calibration and Debug The debug over CAN scheme supports the following features: • Supports operation through M_CAN0 or M_CAN1 interfaces – Makes use of M_CAN debug enhancements – Debug message selected by filter configuration EFEC[2:0]=111 • Allows debug of hardware where JTAG access is not available •...
Page 256: Nexus Aurora Router (Nar)
Calibration and Debug RM0400 instructions for the different Nexus clients are shown in Table 90. After the enable instruction is received, the development tool has access to the Nexus registers of the selected client. Table 90. Nexus client JTAG enable instructions Module Enable instruction Opcode...
Page 257: Table 91. Pd Nar Clients
RM0400 Calibration and Debug Figure 43. NAR block diagram The PD NAR module has two clients with client index 1and 3. All other client indexes are not connected. Table 91 contains the client connections and the corresponding NAR client index. The NAR client index is used in the NAR_STCR, NAR_CSSR, and NAR_CDR registers.
Page 258: Nexus Clients
Calibration and Debug RM0400 Table 91. PD NAR clients(Continued) Client index Client Nexus source trace ID (SRC) Beats per client (Bn) — — — — — — — — — — — — — — — — — — — —...
Page 259: Core E200Z215An3 Description
RM0400 Core e200z215An3 description Core e200z215An3 description 12.1 Overview of the e200z215An3 core The e200z215An3 is a single-issue 32-bit PowerISA 2.06 VLE compliant design with 32-bit general-purpose registers (GPRs). The e200z215An3 core implements the VLE (variable- length encoding) ISA, providing improved code density. The VLE ISA is further documented in PowerISA 2.06, a separate document.
Page 260: Efpu2 Floating-Point Unit Features
Core e200z215An3 description RM0400 12.2 EFPU2 Floating-Point Unit features • The EFPU2 embedded floating-point unit supports pipelined operation of most floating- point operations, allowing a throughput of one FP operation per cycle, and supports a variety of operations:Supports IEEE754 single-precision data format •...
Page 261: Figure 44. E200Z215An3 Supervisor Mode Programmer's Model Sprs
RM0400 Core e200z215An3 description Figure 44. e200z215An3 Supervisor Mode Programmer’s Model SPRs SUPERVISOR Mode Programmer’s Model SPRs Exception Handling/Control Registers General Registers Save and Restore SPR General Interrupt Vector Prefix General-Purpose Registers Condition IVPR SPRG0 SRR0 SPR 26 SPRG1 SRR1 SPR 27 GPR0 Count Register...
Page 262: Figure 45. E200Z215An3 Supervisor Mode Programmer's Model Dcrs And Pmrs
Core e200z215An3 description RM0400 Figure 45. e200z215An3 Supervisor Mode Programmer’s Model DCRs and PMRs Supervisor Mode Programmer’s Model DCRs and PMRs Nexus3 Debug Performance Moni- Registers User Control DCR 368 Control (read-only) Counters DCR 369 PMR 400 PMR 384 PMR 16 PMGC0 UPMGC0 PMC0...
Page 263: Figure 46. E200Z215An3 User Mode Programmer's Model Sprs
RM0400 Core e200z215An3 description Figure 46. e200z215An3 User Mode Programmer’s Model SPRs USER Mode Programmer’s Model SPRs Cache Register General Registers (Read-only) Debug General-Purpose Condition Register Registers Cache Configuration DEVENT SPR 975 Count GPR0 DDAM SPR 576 L1CFG0 SPR 515 GPR1 L1CFG1 SPR 516...
Page 264: Single-Issue Operation
Core e200z215An3 description RM0400 12.4 Single-issue operation The instruction issue unit attempts to issue an instruction to the execution units each cycle. Source operands for each of the instructions are provided from the GPRs or from the operand feed-forward muxes. Data or resource hazards may create stall conditions that cause instruction issue to be stalled for one or more cycles until the hazard is eliminated.
Page 265 RM0400 Core e200z215An3 description Table 93. EFPU Status and Control Register field descriptions(Continued) Bits Name Description Embedded Floating-point Overflow Sticky Flag FOVFS The FOVFS bit is set to 1 when a floating-point instruction sets the FOVF bit to 1. The (46) FOVFS bit remains set until it is cleared by a mtspr instruction specifying the SPEFSCR.
Page 266: Exceptions
Core e200z215An3 description RM0400 Table 93. EFPU Status and Control Register field descriptions(Continued) Bits Name Description Embedded Floating-point Inexact Exception Enable If the exception is enabled, a Floating-point Round exception is taken if the result of a Floating-point instruction does not result in overflow or underflow, and the result is inexact (FG | FX = 1), or if the result of a Floating-point instruction does result in overflow (FOVF = 1) but Floating-point Overflow exceptions are disabled (FOVFE = 0), or if the FINXE...
Page 267: Exception Syndrome Register (Esr)
RM0400 Core e200z215An3 description Table 94. Exceptions and conditions Interrupt vector Interrupt type Causing conditions offset value none, vector to System reset [p_rstbase[0:29]] Reset || 2’b00 Critical Input 0x00 p_critint_b is asserted and MSR = 1. 1. p_mcp_b transitions from negated to asserted 2.
Page 268: Table 95. Esr Field Descriptions
Core e200z215An3 description RM0400 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 62; Read/Write; Reset: 0x0 Figure 49. Exception Syndrome Register (ESR) The ESR bits are defined in Table Table 95.
Page 269: Machine State Register (Msr)
RM0400 Core e200z215An3 description Table 95. ESR field descriptions(Continued) Bit(s) Name Description Associated interrupt type — Reserved — — Reserved — 12.6.2 Machine State Register (MSR) The Machine State Register defines the state of the processor. The e200z215An3 MSR is shown in Figure 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...
Page 270 Core e200z215An3 description RM0400 Table 96. MSR field descriptions(Continued) Bit(s) Name Description Floating-Point Available 0 Floating point unit is unavailable. The processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. 1 Floating Point unit is available. The processor can execute floating-point instructions. Note: For Zen z215An3, the PowerISA 2.06 floating point unit is not supported in hardware, and an Illegal Instruction exception will be generated for attempted execution of PowerISA 2.06 floating point instructions regardless of the setting of FP.
Page 271: Machine Check Syndrome Register (Mcsr)
RM0400 Core e200z215An3 description 12.6.3 Machine Check Syndrome Register (MCSR) When the processor takes a machine check interrupt, it updates the Machine Check Syndrome Register (MCSR) to differentiate between machine check conditions. The MCSR is shown in Figure 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 572;...
Page 272 Core e200z215An3 description RM0400 Table 97. Machine Check Syndrome Register (MCSR) field descriptions(Continued) Exception Recoverabl Name Description type Data Cache Lock error Indicates a cache control operation or invalidation Async DC_LKERR — operation invalidated one or more lines in a locked way of Mchk the D-Cache for certain situations.
Page 273: Interrupt Vector Prefix Registers (Ivpr)
RM0400 Core e200z215An3 description Table 97. Machine Check Syndrome Register (MCSR) field descriptions(Continued) Exception Recoverabl Name Description type Data Mem (DMEM) Parity Error DMEM_RDPERR Async Precise Indicates an uncorrectable error in the DMEM on a CPU Mchk port read access. Data Mem (DMEM) Write Parity Error DMEM_WRPERR Async...
Page 274: Interrupt Definitions
Core e200z215An3 description RM0400 Vector Base 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 63; Read/Write Figure 52. Zen Interrupt Vector Prefix Register (IVPR) The IVPR fields are defined in Table Table 98.
Page 275: Table 100. Machine Check Interrupt—Register Settings
RM0400 Core e200z215An3 description 1. Clearing of DE is optionally supported by control in HID0. The MSR bit is not automatically cleared by a Critical Input interrupt, but it can be configured to be cleared via the HID0 register (HID0 CICLRDE 12.6.5.2 Machine Check Interrupt (offset 0x10)
Page 276: Table 102. Instruction Storage Interrupt—Register Settings
Core e200z215An3 description RM0400 Table 101. Data Storage Interrupt—register settings(Continued) Register Setting description SPV 0 — — — PMM 0 — Access: [ST], [SPV], VLEMI. All other bits cleared. MCSR Unchanged DEAR For Access Control exceptions, set to the effective address of the access that caused the violation. Vector IVPR || 0x20...
Page 277: Table 103. External Input Interrupt—Register Settings
RM0400 Core e200z215An3 description Table 103. External Input Interrupt—register settings Register Setting description Set to the effective address of the instruction that the processor would have attempted to execute next SRR0 if no exception conditions were present. SRR1 Set to the contents of the MSR at the time of the interrupt SPV 0 —...
Page 278: Table 105. Program Interrupt—Register Settings
Core e200z215An3 description RM0400 12.6.5.7 Program Interrupt (offset 0x60) A program interrupt occurs when no higher priority exception exists and one or more of the following exception conditions occur: • Illegal Instruction exception • Privileged Instruction exception • Trap exception The e200z215An3 will invoke an Illegal Instruction program exception on attempted execution of the following instructions: •...
Page 279: Table 106. System Call Interrupt—Register Settings
RM0400 Core e200z215An3 description 12.6.5.8 System Call Interrupt (offset 0x80) A System Call interrupt occurs when a System Call (se_sc) instruction is executed and no higher priority exception exists. Table 106 lists register settings when a System Call interrupt is taken. Table 106.
Page 280: Table 108. System Reset Interrupt—Register Settings
Core e200z215An3 description RM0400 Table 107. Debug Interrupt—register settings(Continued) Register Setting description Unconditional Debug Event: Instr. Complete Debug Event: ICMP Branch Taken Debug Event: Interrupt Taken Debug Event: IRPT Critical Interrupt Taken Debug Event: CIRPT Trap Instruction Debug Event: TRAP Instruction Address Compare: {IAC} DBSR...
Page 281: Table 109. Embedded Floating-Point Data Interrupt—Register Settings
RM0400 Core e200z215An3 description Table 108. System Reset Interrupt—register settings(Continued) Register Setting description Cleared DEAR Undefined Vector [p_rstbase[0:29]] || 2’b00 12.6.5.11 Embedded Floating-point Data Interrupt (offset 0xA0) The Embedded Floating-point Data interrupt is taken if no higher priority exception exists and an EFPU Floating-point Data exception is generated.
Page 282: Table 111. Performance Monitor Interrupt—Register Settings
Core e200z215An3 description RM0400 Table 110. Embedded Floating-point Round Interrupt—register settings(Continued) Register Setting description SPV, VLEMI. All other bits cleared. MCSR Unchanged DEAR Unchanged Vector IVPR || 0xB0 0:23 12.6.5.13 Performance Monitor Interrupt (offset 0x70) A performance monitor interrupt that may be generated by an enabled condition or event. An enabled condition or event is as follows: A PMCx register overflow condition occurs with the following settings: •...
Page 283: System Integration Unit Lite2 (Siul2)
RM0400 System Integration Unit Lite2 (SIUL2) System Integration Unit Lite2 (SIUL2) 13.1 Introduction 13.1.1 Overview The System Integration Unit Lite2 (SIUL2) provides control over all the I/O ports on this device and supports seven ports with 16 bits of bidirectional, general-purpose input and output signals.
Page 284: Figure 53. Siul2 Block Diagram
System Integration Unit Lite2 (SIUL2) RM0400 Figure 53. SIUL2 block diagram SIUL2 Module IP Modules Pad Control and Pin Muxing MSCR Registers GPIO Pads Data Registers Master Interrupt/DMA Request Interrupt Controller Interrupt - Configuration - Glitch Filter MCU Specific (UDR) Registers Misc.
Page 285: Features
RM0400 System Integration Unit Lite2 (SIUL2) 13.1.2 Features The SIUL2 supports these distinctive features: • 7 GPIO ports with data control – Drive data to up to 16 independent I/O channels – Sample data from up to 16 independent I/O channels •...
Page 286: Memory Map And Register Description
System Integration Unit Lite2 (SIUL2) RM0400 13.2 Memory map and register description This section provides a detailed description of all registers accessible in the SIUL2 module. 13.2.1 Memory map Table 112 gives an overview of the SIUL2 registers implemented. Table 112. SIUL2 memory map Address Register name Location...
Page 287: Register Descriptions
RM0400 System Integration Unit Lite2 (SIUL2) Table 112. SIUL2 memory map(Continued) Address Register name Location offset SIUL2 Interrupt Filter Clock Prescaler 0x00C0 on page 296 (SIUL2_IFCPR) 0x00C4– Reserved 0x023F SIUL2 I/O Pin Multiplexed Signal Configuration Register 0–I/O 0x0240– Pin Multiplexed Signal Configuration Register 511 32 32/16/8 on page 297 0xA3C...
Page 288: Table 113. Siul2_Midr1 Field Descriptions
System Integration Unit Lite2 (SIUL2) RM0400 13.2.2.1 SIUL2 MCU ID Register #1 (SIUL2_MIDR1) This register contains identification information about the device.The reset values are: • eTQFP80: 0x5726_1400 • eTQFP100: 0x5726_2400 Address: 0x0004 Access: Read-only PARTNUM Reset MAJOR_MASK MINOR_MASK Reset Figure 54. SIUL2 MCU ID Register #1 (SIUL2_MIDR1) 1.
Page 289: Table 115. Siul2_Midr2 Field Description
1. Values are set at factory and cannot be modified. Table 115. SIUL2_MIDR2 field description Field Description Manufacturer: 0 Reserved 1 STMicroelectronics Coarse granularity for Flash memory size. Needs to be combined with FLASH_SIZE_2 to calculate the actual memory size: 0b000016 KB 0b000132 KB 0b001064 KB 0b0011128 KB 1–4...
Page 290: Table 116. Siul2_Disr0 Field Descriptions
System Integration Unit Lite2 (SIUL2) RM0400 Table 115. SIUL2_MIDR2 field description(Continued) Field Description ASCII character in MCU Part Number: 16–23 0x4CL FAMILYNUM All other values reserved for future use. 24–31 Reserved 13.2.2.3 SIUL2 DMA/Interrupt Status Flag Register 0 (SIUL2_DISR0) The DMA/Interrupt Status Register contains flag bits that record an event on the external IRQ pins.
Page 291: Table 117. Siul2_Direr0 Field Descriptions
RM0400 System Integration Unit Lite2 (SIUL2) Table 116. SIUL2_DISR0 field descriptions(Continued) Field Description Reserved 28–31 External Interrupt Status Flag x—This flag can be cleared only by writing 1. Writing 0 has no EIF3 effect. If enabled (SIUL2_DIRER[x]), EIF[x] causes an interrupt or DMA request. EIF2 0 No interrupt or DMA event has occurred on the pad EIF1...
Page 292: Table 118. Siul2_Dirsr0 Field Descriptions
System Integration Unit Lite2 (SIUL2) RM0400 Table 117. SIUL2_DIRER0 field descriptions(Continued) Field Description Reserved 28–31 EIRE3 External Interrupt or DMA Request Enable x EIRE2 0 Interrupt or DMA requests from the corresponding EIF[x] bit are disabled 1 Set EIF[x] bit causes either a DMA or an interrupt request depending on SIUL2_DIRSR EIRE1 EIRE0 13.2.2.5...
Page 293: Table 119. Siul2_Ireer0 Field Descriptions
RM0400 System Integration Unit Lite2 (SIUL2) Table 118. SIUL2_DIRSR0 field descriptions(Continued) Field Description Reserved 28–31 DMA/Interrupt Request Select Register—Selects between DMA request or external interrupt DIRS3 request when an edge-triggered event occurs on the corresponding pin. DIRS2 0 Interrupt request is selected DIRS1 1 DMA request is selected DIRS0...
Page 294: Table 120. Siul2_Ifeer0 Field Descriptions
System Integration Unit Lite2 (SIUL2) RM0400 13.2.2.7 SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0) This register is used to enable falling-edge triggered events on the corresponding interrupt pads. Address: 0x0030 Access: User read/write Reset IFEE IFEE IFEE IFEE IFEE IFEE Reset Figure 60.
Page 295: Table 121. Siul2_Ifer0 Field Descriptions
RM0400 System Integration Unit Lite2 (SIUL2) Address: 0x0038 Access: User read/write Reset IFE1 IFE5 IFE3 IFE2 IFE1 IFE0 Reset Figure 61. SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0) Table 121. SIUL2_IFER0 field descriptions Field Description 0–20 Reserved Enable digital glitch filter on the interrupt pad input. 0 Filter is disabled IFE10 1 Filter is enabled...
Page 296: Table 122. Siul2_Ifmcr0 Field Descriptions
System Integration Unit Lite2 (SIUL2) RM0400 Table 122. SIUL2_IFMCR0 field descriptions Field Description Maximum Interrupt Filter Counter setting MAXCNTx can be 0 to 15 For MAXCNTx = 0, 1, 2, the filter behaves as ALL PASS filter For MAXCNTx = 3, 4, 5, ... 15, filter period = TCK*MAXCNTx + n*TCK (n = -1 to 3) TCK: Prescaled filter clock period, which is IRC clock prescaled to IFCP value, specified in 28–31...
Page 297: Figure 64. Mscr I/O Pin And Ip Block Port Connectivity
RM0400 System Integration Unit Lite2 (SIUL2) independent of the others, except in the case of an LVDS configuration, where two MSCRs must be configured together in this mode. The MSCRs are divided into two sets: • I/O pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0– SIUL2_MSCR_IO_511) •...
Page 298: Table 124. Siul2_Mscr_Io_0–Siul2_Mscr_Io_511 Field Description
System Integration Unit Lite2 (SIUL2) RM0400 Address: 0x0240–0x0A3C Access: User read/write OERC SMC APC Reset Reset Figure 65. I/O Pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0– SIUL2_MSCR_IO_511) Table 124. SIUL2_MSCR_IO_0–SIUL2_MSCR_IO_511 field description Field Description 0–1 Reserved Output Edge Rate Control—Used only when the associated destination is a chip pin. Specifies the driver strength of the associated pin.
Page 299: Table 125. I/O Mscr Reset State Exceptions
RM0400 System Integration Unit Lite2 (SIUL2) Table 124. SIUL2_MSCR_IO_0–SIUL2_MSCR_IO_511 field description (Continued) Field Description Input Buffer Enable—Used only when the associated destination is a chip pin. Enables the associated pin’s input buffer. 0 Disabled 1 Enabled Input Hysteresis—Used only when the associated destination is a chip pin. Enables input hysteresis for the associated pin.
Page 300: Table 126. Siul2_Mscr_Mux_512–Siul2_Mscr_Mux_1023 Field Description
System Integration Unit Lite2 (SIUL2) RM0400 Table 125. I/O MSCR reset state exceptions(Continued) Port Critical function WPDE WPUE PA[7] 0x0001 PA[8] 0x0001 PA[9] 0x0001 PA[14] — PC[10:15] — PD[6:7] — PE[12] — PF[13] — 13.2.2.11.2 Multiplexed Signal Configuration Registers for Multiplexed Input Selection (SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023) The multiplexed input selection MSCR definition is given in Figure...
Page 301: Table 127. Siul2_Gpdo0–Siul2_Gpdo511 Field Description
RM0400 System Integration Unit Lite2 (SIUL2) Table 126. SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023 field description (Continued) Field Description 17–23 Reserved Source Signal Select—Selects which source signal is connected to the associated destination (chip pin or module port). For a chip pin, the source signals are outputs from module ports. For a 24–31 module port, the source signals are either outputs from module ports or inputs from chip pins.
Page 302: Table 128. Siul2_Gpdi0–Siul2_Gpdi511 Field Description
System Integration Unit Lite2 (SIUL2) RM0400 Address: 0x1500–0x16FF Access: User read Reset Figure 68. SIUL2 GPIO Pad Data Input Registers (SIUL2_GPDI0–SIUL2_GPDI511) Table 128. SIUL2_GPDI0–SIUL2_GPDI511 field description Field Description Pad Data In—This bit stores the value of the external GPIO pad associated with this register. 0 The value of the data in signal for the corresponding GPIO pad is logic low PDI[x] 1 The value of the data in signal for the corresponding GPIO pad is logic high...
Page 303: Table 130. Siul2_Pgpdi0 Field Description
RM0400 System Integration Unit Lite2 (SIUL2) 13.2.2.15 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI0_1– SIUL2_PGPDI30_31) These registers hold the synchronized input value from the pads. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration.
Page 304: Functional Description
System Integration Unit Lite2 (SIUL2) RM0400 Table 131. SIUL2_MPGPDO0 field description Field Description Mask Field—Each bit corresponds to one data bit in the MPPDO[x] register at the same bit 0–15 location. MASK[x] 0 The associated bit value in the MPPDO[x] field is ignored [0:15] 1 The associated bit value in the MPPDO[x] field is written Masked Parallel Pad Data Out—Write the data register that stores the value to be driven on the...
Page 305: General Purpose Input Or Output Pads (Gpio)
RM0400 System Integration Unit Lite2 (SIUL2) operation. This is achieved by grouping all of the above functions into a single register for each pad on the device, and allows each pad to be configured with a single write to one register and allowing simplified duplication of software for each pad with indexed changes for each pad.
Page 306: External Interrupts/Dma Requests (Eirq Pins)
System Integration Unit Lite2 (SIUL2) RM0400 13.3.4 External interrupts/DMA requests (EIRQ pins) The SIUL2 supports three external interrupts which can be allocated to any pad necessary at the MCU level. This allocation is fixed per MCU. The SIUL2 supports two interrupt vectors to the interrupt controller of the MCU. Each interrupt vector can support three external interrupt sources from the device pads.
Page 307 RM0400 System Integration Unit Lite2 (SIUL2) 13.3.4.1 External interrupt initialization When an external interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt request, during pin interrupt initialization, the user must do the following: •...
Page 308: Figure 74. Interrupt To Vector Mapping At Mcu Level
System Integration Unit Lite2 (SIUL2) RM0400 Figure 74. Interrupt to vector mapping at MCU level 308/2058 DocID027809 Rev 4...
Page 309: Crossbar Switch (Xbar)
RM0400 Crossbar Switch (XBAR) Crossbar Switch (XBAR) 14.1 Introduction This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a hardware interconnect matrix. This structure allows all bus masters to access different bus slaves simultaneously with no interference while providing arbitration among the bus masters when they access the same slave.
Page 310: Table 132. Xbar Memory Map
Crossbar Switch (XBAR) RM0400 Table 132. XBAR memory map Address Width Register name Access Reset value Location offset (hex) (in bits) XBAR Priority Register Slave 0 See Chip on page 310 (XBAR_PRS0) Config XBAR Control Register 0 (XBAR_CRS0) 0000_0000h on page 313 XBAR Priority Register Slave 1 See Chip on page 310...
Page 311: Table 133. Xbar_Prsn Field Descriptions
RM0400 Crossbar Switch (XBAR) Offset: 0x0000 + n*0x100 (n = 0 to 7) Access: Supervisor read-only Reset See Chip Configuration section for this device’s reset values. Reset See Chip Configuration section for this device’s reset values. Figure 75. Priority Registers Slave (XBAR_PRSn) Table 133.
Page 312 Crossbar Switch (XBAR) RM0400 Table 133. XBAR_PRSn field descriptions(Continued) Field Description This read-only bit is reserved and always has the value zero. Reserved Master 4 priority. Sets the arbitration priority for this port on the associated slave port: 000 This master has level 1 (highest) priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port.
Page 313: Table 134. Xbar_Crsn Field Descriptions
RM0400 Crossbar Switch (XBAR) Table 133. XBAR_PRSn field descriptions(Continued) Field Description This read-only bit is reserved and always has the value zero. Reserved Master 0 priority. Sets the arbitration priority for this port on the associated slave port: 000 This master has level 1 (highest) priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port.
Page 314: Functional Description
Crossbar Switch (XBAR) RM0400 Table 134. XBAR_CRSn field descriptions(Continued) Field Description High Priority Enable Determines if Master x is able to temporarily elevate it's request to the slave to high priority status. This can help reduce the amount of time the high priority requesting master must wait to 8–15 gain control of the slave.
Page 315: General Operation
RM0400 Crossbar Switch (XBAR) 14.2.1 General operation When a master sends an access to the crossbar switch, the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. It is possible to make single-clock (zero wait state) accesses through the crossbar.
Page 316: Arbitration
Crossbar Switch (XBAR) RM0400 14.2.3 Arbitration The crossbar switch supports two arbitration schemes: a simple fixed-priority comparison algorithm and a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port. 14.2.3.1 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level in the XBAR_PRSn (priority registers).
Page 317: Initialization/Application Information
RM0400 Crossbar Switch (XBAR) 14.2.3.3 Priority assignment Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within the priority registers (XBAR_PRSn), the crossbar switch responds with a bus error and the registers are not updated.
Page 318: Peripheral Bridge
Peripheral Bridge RM0400 Peripheral Bridge 15.1 Introduction The peripheral bridge converts the crossbar switch interface to an interface that can access a majority of peripherals on the device. The peripheral bridge occupies a 64 MB portion of the address space. (Not all peripheral slots may be used.
Page 319: Master Privilege Registers (Aips_Mpra)
RM0400 Peripheral Bridge Table 135. Peripheral bridge memory map(Continued) Offset Width Register Location address (bits) 0x104 Peripheral Access Control Register B (AIPS_PACRB) on page 320 0x108 Peripheral Access Control Register C (AIPS_PACRC) on page 320 0x10C Peripheral Access Control Register D (AIPS_PACRD) on page 320 0x110 Reserved...
Page 320: Peripheral Access Control Registers (Aips_Pacrx)
Peripheral Bridge RM0400 Table 136. MPROTn field descriptions(Continued) Field Description Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. Master privilege level Determines how the privilege level of the master is determined.
Page 321: Off-Platform Peripheral Access Control Registers (Aips_Opacrx)
RM0400 Peripheral Bridge Figure 80. PACRn fields Table 138. PACRn field descriptions Field Description Reserved, should be cleared Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses.
Page 322 Peripheral Bridge RM0400 Table 139. OPACR memory map(Continued) Offset Register [0:3] [4:7] [8:11] [12:15] [16:19] [20:23] [24:27] [28:31] OPACR OPACR OPACR OPACR OPACR OPACR OPACR OPACR 0x014C OPACRD OPACR OPACR OPACR OPACR OPACR OPACR OPACR OPACR 0x0150 OPACRE OPACR OPACR OPACR OPACR OPACR...
Page 323: Figure 81. Off-Platform Peripheral Access Control Registers (Aips_Opacra–Af)
RM0400 Peripheral Bridge Table 139. OPACR memory map(Continued) Offset Register [0:3] [4:7] [8:11] [12:15] [16:19] [20:23] [24:27] [28:31] OPACR OPACR OPACR OPACR OPACR OPACR OPACR OPACR 0x0198 OPACRW OPACR OPACR OPACR OPACR OPACR OPACR OPACR OPACR 0x019C OPACRX OPACR OPACR OPACR OPACR OPACR...
Page 324: Functional Description
Peripheral Bridge RM0400 Table 140. OPACRn field descriptions Field Description Reserved, should be cleared Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set.
Page 325: System Memory Protection Unit (Smpu)
RM0400 System Memory Protection Unit (SMPU) System Memory Protection Unit (SMPU) 16.1 Overview The System Memory Protection Unit (SMPU) provides hardware access control for system bus memory references. The SMPU concurrently monitors and evaluates system bus transactions using pre-programmed region descriptors that define memory spaces and their access rights.
Page 326: Figure 83. Smpu Block Diagram
System Memory Protection Unit (SMPU) RM0400 Figure 83. SMPU block diagram Slave Port n Internal Address Phase Signals Peripheral Bus Access R egion Evaluation D escriptor 0 M acro Access R egion Evaluation D escriptor 1 M acro Access R egion Evaluation D escriptor M acro...
Page 327: Features
RM0400 System Memory Protection Unit (SMPU) 16.3 Features The SMPU feature set includes: • Supports up to 24 program-visible 128-bit region descriptors, accessible as four 32-bit words each. (Specific module instances may support fewer than 24). – Each region descriptor defines an arbitrarily sized space, aligned anywhere in memory –...
Page 328: Table 141. Smpux Memory Map
System Memory Protection Unit (SMPU) RM0400 Table 141. SMPUx memory map Absolute Width Register name Access Reset value Section address (hex) (in bits) FC01_0000 SMPU0_CESR0 0000_8002h Section 16.4.2.1 FC01_0004 SMPU0_CESR1 0000_8003h Section 16.4.2.2 FC01_0100 SMPU0_EAR0 0000_0000h Section 16.4.2.3 FC01_0104 SMPU0_EDR0 0000_0080h Section 16.4.2.4 FC01_0108...
Page 329 RM0400 System Memory Protection Unit (SMPU) Table 141. SMPUx memory map(Continued) Absolute Width Register name Access Reset value Section address (hex) (in bits) FC01_0400 SMPU0_RGD0_WORD0 0000_0000h Section 16.4.2.5 FC01_0404 SMPU0_RGD0_WORD1 0000_0000h Section 16.4.2.6 FC01_0408 SMPU0_RGD0_WORD2_FMT0 0000_0000h Section 16.4.2.7 FC01_0408 SMPU0_RGD0_WORD2_FMT1 0000_0000h Section 16.4.2.8 FC01_040C...
Page 330 System Memory Protection Unit (SMPU) RM0400 Table 141. SMPUx memory map(Continued) Absolute Width Register name Access Reset value Section address (hex) (in bits) FC01_046C SMPU0_RGD6_WORD3 0000_0000h Section 16.4.2.9 FC01_0470 SMPU0_RGD7_WORD0 0000_0000h Section 16.4.2.5 FC01_0474 SMPU0_RGD7_WORD1 0000_0000h Section 16.4.2.6 FC01_0478 SMPU0_RGD7_WORD2_FMT0 0000_0000h Section 16.4.2.7 FC01_0478...
Page 331: Register Descriptions
RM0400 System Memory Protection Unit (SMPU) 16.4.2 Register descriptions 16.4.2.1 Control/Error Status Register 0 (SMPU0_CESR0) Address SMPU0_CESR0 – FC01_0000h base + 0h offset = FC01_0000h Access: Supervisor read/write MERR Reset Reset Figure 84. Control/Error Status Register 0 (SMPU0_CESR0) Table 142. SMPU0_CESR0 field descriptions Field Description Master n error, where the bus master number matches the bit number...
Page 332: Table 143. Smpu0_Cesr1 Field Descriptions
System Memory Protection Unit (SMPU) RM0400 16.4.2.2 Control/Error Status Register 1 (SMPU0_CESR1) Address SMPU0_CESR1 – FC01_0000h base + 4h offset = FC01_0004h Access: Supervisor read-only MEOVR Reset NRGD Reset Figure 85. Control/Error Status Register 1 (SMPU0_CESR1) Table 143. SMPU0_CESR1 field descriptions Field Description Master n error overrun, where the bus master number matches the bit number...
Page 333: Table 144. Smpu0_Earn Field Descriptions
RM0400 System Memory Protection Unit (SMPU) Address SMPU0_EARn – FC01_0100h + (8d × n), where n = 0d to 15d Access: Supervisor read-only EADDR Reset EADDR Reset Figure 86. Error Address Register, Bus Master n (SMPU0_EARn) Table 144. SMPU0_EARn field descriptions Field Description 0–31...
Page 334: Table 145. Smpu0_Edrn Field Descriptions
System Memory Protection Unit (SMPU) RM0400 Table 145. SMPU0_EDRn field descriptions Field Description Error access control detail Indicates the region descriptor with the access error, where the region descriptor number matches the bit number. 0–23 If EDRn contains a captured error and EACD is all zeroes, an access did not hit in any region EACD descriptor.
Page 335: Table 147. Smpu0_Rgdn_Word1 Field Descriptions
RM0400 System Memory Protection Unit (SMPU) 16.4.2.6 Region Descriptor n, Word 1 (SMPU0_RGDn_WORD1) Address SMPU0_RGDn_WORD1 – FC01_0404h + (16 × n), where n = 0 to 11 Access: Supervisor read/write ENDADDR Reset ENDADDR Reset Figure 89. Region Descriptor n, Word 1 (SMPU0_RGDn_WORD1) Table 147.
Page 336: Table 148. Smpu0_Rgdn_Word2_Fmt0 Field Descriptions
System Memory Protection Unit (SMPU) RM0400 Access: Address: SMPU0_RGDn_WORD2_FMT0 – FC01_0408h + (16 × n), where n = 0 to 11 Supervisor read/write Reset M10P M11P M12P M13P M14P M15P Reset Figure 90. Region Descriptor n, Word 2 Format 0 (SMPU0_RGDn_WORD2_FMT0) Table 148.
Page 337: Figure 91. Region Descriptor N, Word 2 Format 1 (Smpu0_Rgdn_Word2_Fmt1)
RM0400 System Memory Protection Unit (SMPU) Table 148. SMPU0_RGDn_WORD2_FMT0 field descriptions(Continued) Field Description 26–27 Bus master 13 permissions M13P 28–29 Bus master 14 permissions M14P 30–31 Bus master 15 permissions M15P 16.4.2.8 Region Descriptor n, Word 2 Format 1 (SMPU0_RGDn_WORD2_FMT1) RGD_WORD2 has two formats as determined by the RGD_WORD3[FMT] field.
Page 338: Table 149. Smpu0_Rgdn_Word2_Fmt1 Field Descriptions
System Memory Protection Unit (SMPU) RM0400 Table 149. SMPU0_RGDn_WORD2_FMT1 field descriptions Field Description 0–1 Bus master 0 permission select 2–3 Bus master 1 permission select 4–5 Bus master 2 permission select 6–7 Bus master 3 permission select 8–9 Bus master 4 permission select 10–11 Bus master 5 permission select 12–13...
Page 339: Table 150. Smpu0_Rgdn_Word3 Field Descriptions
RM0400 System Memory Protection Unit (SMPU) 16.4.2.9 Region Descriptor n, Word 3 (SMPU0_RGDn_WORD3) The final word of the SMPU region descriptor contains the valid bit, the format select (FMT), three sets of access permissions flags used when FMT = 1, plus other configuration bits.
Page 340: Functional Description
System Memory Protection Unit (SMPU) RM0400 Table 150. SMPU0_RGDn_WORD3 field descriptions(Continued) Field Description 18–26 This read-only bitfield is reserved and always has the value ‘0’. Reserved Region Descriptor Format This bit selects the configuration format (FMT0 or FMT1) for this region descriptor. Note: A specific module instance of the SMPU may support only the FMT0 format.
Page 341: Figure 93. Smpu Access Evaluation Macro
RM0400 System Memory Protection Unit (SMPU) Figure 93. SMPU access evaluation macro R G D start e nd Address r,w,x ≥ ≤ error hit_b ≥ ≥ E DR A ccess not allow ed (no hit OR error) (hit A N D error) 16.5.1.1 Hit determination To determine if the current reference hits in the given region, two magnitude comparators...
Page 342: Putting It All Together And Error Terminations
System Memory Protection Unit (SMPU) RM0400 Table 151. Protection violation definition Access permissions Access type Protection violation? — Yes, no read permission Instruction fetch read — No, access is allowed — Yes, no read permission Data read — No, access is allowed —...
Page 343: Table 152. Overlapping Region Descriptor Example
RM0400 System Memory Protection Unit (SMPU) maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes. • Modifying a region descriptor—Load the updates into the region descriptor using sequential 32-bit writes. Writing to Word3 re-enables the region descriptor valid bit. The hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes.
Page 344 System Memory Protection Unit (SMPU) RM0400 The space defined by RGD2 with no overlap is a private data and stack area that provides read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared data space for passing data from CP0 to CP1, and the access controls are defined by the logical OR of the two region descriptors.
Page 345: Intelligent Ahb Gasket (Iahbg)
RM0400 Intelligent AHB Gasket (IAHBG) Intelligent AHB Gasket (IAHBG) 17.1 Introduction This section details the intelligent bridging gasket between the fast and slow clock domains. The intelligent operation of the gasket initiates pending reads early and optimizes bursts to recover some of the performance that is lost on a registered interface between different clock domains.
Page 346: Figure 94. Read, Pending Read (1:1 Timing Mode)
Intelligent AHB Gasket (IAHBG) RM0400 Figure 94. Read, pending read (1:1 timing mode) Figure 95. Write, pending read (1:1 timing mode) 346/2058 DocID027809 Rev 4...
Page 347: Figure 96. Burst4 Read (1:1 Timing Mode)
RM0400 Intelligent AHB Gasket (IAHBG) Figure 96. Burst4 read (1:1 timing mode) Figure 97. Burst4 write (1:1 timing mode) 17.2.2 In the 2:1 timing mode the master is running at twice the clock frequency of the slave. The 4:1 mode is not shown because it is very similar to the 2:1 mode. There are different read slots that the pending read transaction can begin executing early, but only the first slot is shown.
Page 348: Figure 98. Read, Pending Read (2:1 Timing Mode)
Intelligent AHB Gasket (IAHBG) RM0400 Figure 98. Read, pending read (2:1 timing mode) 348/2058 DocID027809 Rev 4...
Page 349: Figure 99. Write, Pending Read (2:1 Timing Mode)
RM0400 Intelligent AHB Gasket (IAHBG) Figure 99. Write, pending read (2:1 timing mode) DocID027809 Rev 4 349/2058...
Page 350: Figure 100. Burst4 Read (2:1 Timing Mode)
Intelligent AHB Gasket (IAHBG) RM0400 Figure 100. Burst4 read (2:1 timing mode) 350/2058 DocID027809 Rev 4...
Page 351: Figure 101. Burst4 Write (2:1 Timing Mode)
RM0400 Intelligent AHB Gasket (IAHBG) Figure 101. Burst4 write (2:1 timing mode) 17.2.3 In the 1:2 timing mode, the slave is running at twice the clock frequency of the master. The 1:4 mode is not shown because it is very similar to the 1:2 mode. There are different read slots that the pending read transaction can begin executing early, but only the first slot is shown.
Page 352: Figure 102. Read, Pending Read (1:2 Timing Mode)
Intelligent AHB Gasket (IAHBG) RM0400 Figure 102. Read, pending read (1:2 timing mode) 352/2058 DocID027809 Rev 4...
Page 353: Figure 103. Write, Pending Read (1:2 Timing Mode)
RM0400 Intelligent AHB Gasket (IAHBG) Figure 103. Write, pending read (1:2 timing mode) DocID027809 Rev 4 353/2058...
Page 354: Figure 104. Burst4 Read (1:2 Timing Mode)
Intelligent AHB Gasket (IAHBG) RM0400 Figure 104. Burst4 read (1:2 timing mode) 354/2058 DocID027809 Rev 4...
Page 355: 32 Interface
RM0400 Intelligent AHB Gasket (IAHBG) Figure 105. Burst4 write (1:2 timing mode) 17.2.4 64->32 Interface The 64->32 interface translates a 64-bit access to two 32-bit accesses on the slave side. If there is an hresp on the first 32-bit access to the slave, the iahb_gasket will still do the second 32-bit access.
Page 356 Intelligent AHB Gasket (IAHBG) RM0400 Unaligned bursts are translated to NSEQ. To support initializing ECC in the SRAM where two 32-bit write accesses through the 32->64 gasket needs to get translated to a single 64-bit write access, the master will send aligned (haddr[2]==0) double word transactions with a burst encoding of INCR with length fixed to 2.
Page 357: Interrupt Controller (Intc)
RM0400 Interrupt Controller (INTC) Interrupt Controller (INTC) 18.1 Introduction The INTC: • Provides priority-based preemptive scheduling of interrupt requests • Schedules interrupt requests (IRQs) from software and internal peripherals to one or more processors (PRCs) • Provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support This scheduling scheme is suitable for statically scheduled hard real-time systems.
Page 358: Figure 106. Block Diagram For An Intc With Four Processors
Interrupt Controller (INTC) RM0400 Figure 106. Block diagram for an INTC with four processors INT_SOURCES INTC INTC_SSCIR0 INTC_PSR0 INTC_SSCIR31 INTC_PSR1023 PRC3 ACK3 Priority Tree1 PRC2 ACK2 Priority Tree1 PRC1 ACK1 Priority Tree1 PRC0 ACK0 Priority Tree1 Priority Tree2 Priority Tree2 Priority Tree2 Priority Tree2 Priority Tree3...
Page 359: Features
RM0400 Interrupt Controller (INTC) 18.3 Features • Each peripheral interrupt source is software-steerable to processor 0, processor 1, processor 2, processor 3, or any combination of interrupt request outputs • 32 software-settable interrupt request sources • 10-bit vector – Unique vector for each interrupt request source –...
Page 360: Hardware Vector Mode
Interrupt Controller (INTC) RM0400 the associated LIFO, and updates PRI in the associated INTC_CPR_PRCn with the new priority. 18.4.2 Hardware vector mode In hardware vector mode, the hardware causes the first instruction that will be executed (when handling the interrupt request to the processor) to be an instruction that is specific to that vector.
Page 361: Register Descriptions
RM0400 Interrupt Controller (INTC) Table 154. INTC memory map(Continued) Address offset Register Location 024h INTC Interrupt Acknowledge Register for Processor 1 (INTC_IACKR1) on page 363 028h INTC Interrupt Acknowledge Register for Processor 2 (INTC_IACKR2) on page 363 02Ch INTC Interrupt Acknowledge Register for Processor 3 (INTC_IACKR3) on page 363 030h INTC End Of Interrupt Register for Processor 0 (INTC_EOIR0)
Page 362: Table 155. Intc_Bcr Field Descriptions
Interrupt Controller (INTC) RM0400 Offset: 000h Access: User read/write Reset Reset Figure 107. INTC Block Configuration Register (INTC_BCR) Table 155. INTC_BCR field descriptions Field Description Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. See Section 18.4, Modes of operation, for the details of the handshaking with the processor in each mode.
Page 363: Table 156. Intc_Cprn Field Descriptions
RM0400 Interrupt Controller (INTC) 010h (INTC_CPR0) 014h (INTC_CPR1) Offsets: Access: User read/write 018h (INTC_CPR2) 01Ch (INTC_CPR3) Reset Reset Figure 108. INTC Current Priority Register for Processor n (INTC_CPRn) Table 156. INTC_CPRn field descriptions Field Description Priority of the currently executing ISR, according to the field values 63 (highest priority) down to 0 (lowest priority).
Page 364: Table 157. Intc_Iackrn Field Descriptions
Interrupt Controller (INTC) RM0400 Table 157. INTC_IACKRn field descriptions Field Description VTBA Vector table base address. Can be the base address of a vector table of addresses of ISRs. Interrupt vector. Vector of the peripheral or software-settable interrupt request that caused the INTVEC interrupt request to the processor.
Page 365: Table 159. Intc_Sscirn Field Descriptions
RM0400 Interrupt Controller (INTC) Figure 111 shows the structure of the first INTC_SSCIR. The other registers follow the same structure. Offset: 040h Access: User read/write Reset Figure 111. INTC Software Set/Clear Interrupt Registers (INTC_SSCIRn) Table 159. INTC_SSCIRn field descriptions Field Description Set flag bits.
Page 366: Table 160. Intc_Psrn Field Descriptions
Interrupt Controller (INTC) RM0400 Offset: 85Eh Access: User read/write PRC_SEL1023 PRI1023 Reset Figure 113. INTC Priority Select Register 1023 (INTC_PSR1023) Table 160. INTC_PSRn field descriptions Field Description Processor select bits. See Table 161. If an interrupt source is enabled, PRC_SELn[3:0] PRC_SELn selects whether the interrupt request is to be sent to processor 0, processor 1, processor 2, processor 3, or any combination.
Page 367: Functional Description
RM0400 Interrupt Controller (INTC) 18.6 Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. In addition, spaces in the memory map have been reserved for other possible implementations of the INTC. 18.6.1 Interrupt request sources The INTC has two types of interrupt requests, peripheral and software-settable.
Page 368: Priority Management
Interrupt Controller (INTC) RM0400 Any Processor n will be allowed to write to any of the SET bits in the Software Set/Clear Interrupt registers. The CLR bit will only be writable by the Processor n which has been assigned to handle that interrupt request, as determined by the setting of the INTC_PSRn[PRC_SELn] bits.
Page 369: Handshaking With Processor
RM0400 Interrupt Controller (INTC) 18.6.2.1.4 Comparator The comparator logic compares the highest priority output from the associated priority arbitrator subblock with PRI in the associated INTC_CPRn. If the comparator detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the associated processor.
Page 370 Interrupt Controller (INTC) RM0400 even supports processors that always expect an interrupt vector with the interrupt request to them. Refer to Figure 114. A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown Figure 114.
Page 371: Figure 114. Timing Diagram Of Software Vector Mode Handshaking
RM0400 Interrupt Controller (INTC) Figure 114. Timing diagram of software vector mode handshaking clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read INTC_IACKRn write INTC_EOIRn INTVEC in INTC_IACKRn PRI in INTC_CPRn peripheral interrupt request 100 18.6.3.2 Hardware vector mode handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown...
Page 372: Initialization/Application Information
Interrupt Controller (INTC) RM0400 Figure 115. Timing diagram for hardware vector mode handshaking clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read INTC_IACKRn write INTC_EOIRn INTVEC in INTC_IACKRn PRI in INTC_CPRn peripheral interrupt request 100 18.7 Initialization/application information 18.7.1 Initialization flow...
Page 373: Interrupt Exception Handler
RM0400 Interrupt Controller (INTC) 18.7.2 Interrupt exception handler These example interrupt exception handlers excerpts use Power Architecture assembly code. 18.7.2.1 Software vector mode In software vector mode for Power Architecture, there are 16 bytes of vector space available at the single ISR entry point. interrupt_exception_handler: b interrupt_exception_handler_continued# 16 bytes available, branch to continue...
Page 374 Interrupt Controller (INTC) RM0400 code to restore SRR0 and SRR1, restore working registers, and delete stack frame (not shown) vector_table_base_address: address of ISR for interrupt with vector 0 address of ISR for interrupt with vector 1 address of ISR for interrupt with vector 1022 address of ISR for interrupt with vector 1023 ISRn: code to service the interrupt event (not shown)
Page 375: Isr, Rtos, And Task Hierarchy
RM0400 Interrupt Controller (INTC) # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lisr3,INTC_EOIRn@ha# form adjusted upper half of INTC_EOIRn address...
Page 376: Table 162. Order Of Isr Execution Example
Interrupt Controller (INTC) RM0400 is high enough to cause preemption, the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software-settable interrupt requests asserted.
Page 377: Priority Ceiling Protocol
RM0400 Interrupt Controller (INTC) 18.7.5 Priority ceiling protocol 18.7.5.1 Elevating priority The PRI field in INTC current priority register (INTC_CPRn) is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol therefore allows coherent accesses of the ISRs to that shared resource.
Page 378: Figure 116. Interrupt Request Block Diagram
Interrupt Controller (INTC) RM0400 wrteei 1# enable external interrupts to the Processor 18.7.5.2.1.1 Interrupt request to processor Referencing Figure 106, the interrupt request logic to the processor is shown in Figure 116. Figure 116. Interrupt request block diagram > INT_SOURCES writeCPRn Interrupt IRQn...
Page 379: Selecting Priorities According To Request Rates And Deadlines
RM0400 Interrupt Controller (INTC) Figure 117. Timing diagram of raised priority preserved Clock Interrupt request to processor msree Write INTC_CPRn INTVEC in INTC_ACKRn 0x108 0x208 PRI in INTC_CPRn Peripheral interrupt request 100 Peripheral interrupt request 200 Table 163. Raised priority preserved events Event Description Peripheral interrupt request 200 of priority 2 asserts during execution of ISR108 running at priority 1.
Page 380: Software-Settable Interrupt Requests
Interrupt Controller (INTC) RM0400 Reducing the number of priorities does cause some priority inversion, which reduces the processor’s ability to meet its deadlines. However, reducing the number of priorities can reduce the size and latency through the interrupt controller. It also allows easier management of ISRs with similar deadlines that share a resource.
Page 381: Negating An Interrupt Request Outside Of Its Isr
RM0400 Interrupt Controller (INTC) inefficiencies with an ISR whose work spans multiple priorities (as described in Section 18.7.7.1, Scheduling a lower priority portion of an ISR) is to lower the current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
Page 382: Interrupt Sources
Interrupt Controller (INTC) RM0400 oldCPRn = INTC_CPRn; # save INTC_CPRn (branch to the pop_lifo) pop_lifo: store INTC_EIORn # pop INTC_CPR from LIFO, examine PRI, etc... examine INTC_CPRn[PRI], and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo branch to push_lifo When the examination is complete, the LIFO can be restored using this code sequence:...
Page 383: Introduction
RM0400 Enhanced Direct Memory Access (eDMA) Enhanced Direct Memory Access (eDMA) 19.1 Introduction The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes a DMA engine that performs source- and destination-address calculations, and the actual data-movement operations, along with local memory containing transfer control descriptors for each of the 16 channels.
Page 384: Modes Of Operation
Enhanced Direct Memory Access (eDMA) RM0400 • 16-channel implementation that performs complex data transfers with minimal intervention from a host processor – Internal data buffer, used as temporary storage to support 16- and 32-byte burst transfers – Connections to the crossbar switch for bus mastering the data movement •...
Page 385: Wait Mode
RM0400 Enhanced Direct Memory Access (eDMA) 19.2.3 Wait mode Before entering Wait mode the DMA attempts to complete its current transfer. After the transfer completes the device enters Wait mode. 19.3 Memory map/register definition The eDMA’s programming model is partitioned into two regions: •...
Page 386 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) FC0A_001D Clear Error Register (DMA_CERR) on page 407 (always reads 0) FC0A_001E Set START Bit Register (DMA_SSRT) on page 408 (always reads 0) Clear DONE Status Bit Register...
Page 387 RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) Channel 10 Priority Register FC0A_010A on page 415 (DMA_DCHPRI10) Channel 11 Priority Register FC0A_010B on page 415 (DMA_DCHPRI11) Channel 12 Priority Register FC0A_010C...
Page 388 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) Channel 13 Master ID Register FC0A_014D on page 415 (DMA_DCHMID13) Channel 14 Master ID Register FC0A_014E on page 415 (DMA_DCHMID14) Channel 15 Master ID Register FC0A_014F...
Page 389 RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) TCD1 Minor Byte Count (Minor Loop Disabled) 0000_000Xh on page 419 (DMA_TCD1_NBYTES_MLNO) FC0A_1028 (DMA_TCD1_NBYTES_MLOFFNO) 0000_000Xh on page 419 (DMA_TCD1_NBYTES_MLOFFYES) 0000_000Xh on page 420...
Page 390 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) FC0A_105E (DMA_TCD2_CSR) 000Xh on page 427 TCD3 Source Address FC0A_1060 0000_000Xh on page 416 (DMA_TCD3_SADDR) TCD3 Transfer Attributes FC0A_1064 000Xh on page 417...
Page 391 RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) FC0A_1098 (DMA_TCD4_DLASTSGA) 0000_000Xh on page 425 (DMA_TCD4_BITER_ELINKYES) 000Xh on page 425 FC0A_109C (DMA_TCD4_BITER_ELINKNO) 000Xh on page 426 FC0A_109E (DMA_TCD4_CSR) 000Xh on page 427...
Page 392 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) (DMA_TCD6_CITER_ELINKYES) 000Xh on page 422 TCD6 Current Minor Loop Link, Major FC0A_10D4 Loop Count (Channel Linking Disabled) 000Xh on page 423 (DMA_TCD6_CITER_ELINKNO)
Page 393 RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) (DMA_TCD8_NBYTES_MLNO) 0000_000Xh on page 419 FC0A_1108 (DMA_TCD8_NBYTES_MLOFFNO) 0000_000Xh on page 419 (DMA_TCD8_NBYTES_MLOFFYES) 0000_000Xh on page 420 FC0A_110C (DMA_TCD8_SLAST) 0000_000Xh on page 421 FC0A_1110 (DMA_TCD8_DADDR)
Page 394 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) TCD10 Transfer Attributes FC0A_1144 000Xh on page 417 (DMA_TCD10_ATTR) TCD10 Signed Source Address Offset FC0A_1146 000Xh on page 418 (DMA_TCD10_SOFF) (DMA_TCD10_NBYTES_MLNO) 0000_000Xh...
Page 395 RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) FC0A_117E (DMA_TCD11_CSR) 000Xh on page 427 TCD12 Source Address FC0A_1180 0000_000Xh on page 416 (DMA_TCD12_SADDR) TCD12 Transfer Attributes FC0A_1184 000Xh on page 417...
Page 396 Enhanced Direct Memory Access (eDMA) RM0400 Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) FC0A_11B8 (DMA_TCD13_DLASTSGA) 0000_000Xh on page 425 (DMA_TCD13_BITER_ELINKYES) 000Xh on page 425 FC0A_11BC (DMA_TCD13_BITER_ELINKNO) 000Xh on page 426 FC0A_11BE (DMA_TCD13_CSR) 000Xh on page 427...
Page 397: Control Register (Dma_Cr)
RM0400 Enhanced Direct Memory Access (eDMA) Table 164. DMA memory map(Continued) Absolute Width address Register name Access Reset value Location (in bits) (hex) (DMA_TCD15_CITER_ELINKYES) 000Xh on page 422 TCD15 Current Minor Loop Link, Major FC0A_11F4 Loop Count (Channel Linking Disabled) 000Xh on page 423 (DMA_TCD15_CITER_ELINKNO)
Page 398: Table 165. Dma_Cr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0400 Table 165. DMA_CR field descriptions Field Description 0–13 This read-only field is reserved and always has the value zero. Reserved Cancel transfer 0 Normal operation 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish.
Page 399: Error Status Register (Dma_Es)
RM0400 Enhanced Direct Memory Access (eDMA) Table 165. DMA_CR field descriptions(Continued) Field Description Enable debug 0 When in Debug mode the DMA continues to operate. EDBG 1 When in Debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.
Page 400: Enable Request Register Low (Dma_Erql)
Enhanced Direct Memory Access (eDMA) RM0400 Table 166. DMA_ES field descriptions(Continued) Field Description Channel priority error 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique. 18–23 Error channel number and/or last recorded error cancelled transfer ERRCHN Source address error...
Page 401: Table 167. Dma_Erql Field Descriptions
RM0400 Enhanced Direct Memory Access (eDMA) request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQL. DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted.
Page 402: Enable Error Interrupt Register Low (Dma_Eeil)
Enhanced Direct Memory Access (eDMA) RM0400 Table 167. DMA_ERQL field descriptions(Continued) Field Description Enable DMA Request 7 0 The DMA request signal for the corresponding channel is disabled ERQ7 1 The DMA request signal for the corresponding channel is enabled Enable DMA Request 6 0 The DMA request signal for the corresponding channel is disabled ERQ6...
Page 403: Table 168. Dma_Eeil Field Descriptions
RM0400 Enhanced Direct Memory Access (eDMA) Address: FC0A_0000 + 0x0014 Access: User read/write Reset R EEI Reset Figure 122. Enable Error Interrupt Register Low (DMA_EEIL) Table 168. DMA_EEIL field descriptions Field Description Enable error interrupt 15 0 The error signal for corresponding channel does not generate an error interrupt EEI15 1 The assertion of the error signal for corresponding channel generates an error interrupt request Enable error interrupt 14...
Page 404: Set Enable Request Register (Dma_Serq)
Enhanced Direct Memory Access (eDMA) RM0400 Table 168. DMA_EEIL field descriptions(Continued) Field Description Enable error interrupt 5 0 The error signal for corresponding channel does not generate an error interrupt EEI5 1 The assertion of the error signal for corresponding channel generates an error interrupt request Enable error interrupt 4 0 The error signal for corresponding channel does not generate an error interrupt EEI4...
Page 405: Clear Enable Request Register (Dma_Cerq)
RM0400 Enhanced Direct Memory Access (eDMA) Table 169. DMA_SERQ field descriptions(Continued) Field Description Set all enable requests 0Set only those ERQ bits specified in the SERQ field SAER 1Set all bits in ERQL 2–7 Set enable request SERQ Sets the corresponding bit in ERQL 19.3.6 Clear Enable Request Register (DMA_CERQ) The Clear Enable Request Register (DMA_CERQ) provides a simple memory-mapped...
Page 406: Clear Enable Error Interrupt Register (Dma_Ceei)
Enhanced Direct Memory Access (eDMA) RM0400 Address: FC0A_0000 + 0x001A Access: User write-only SAEE SEEI Reset Figure 125. Set Enable Error Interrupt Register (DMA_SEEI) Table 171. DMA_SEEI field descriptions Field Description 0Normal operation 1No operation, ignore bits 1–7 of this register Sets all enable error interrupts 0Set only those EEI bits specified in the SEEI field.
Page 407: Clear Interrupt Request Register (Dma_Cint)
RM0400 Enhanced Direct Memory Access (eDMA) 19.3.9 Clear Interrupt Request Register (DMA_CINT) The Clear Interrupt Request Register (DMA_CINT) provides a simple, memory-mapped mechanism to clear a given bit in the INTL to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INTL to be cleared.
Page 408: Set Start Bit Register (Dma_Ssrt)
Enhanced Direct Memory Access (eDMA) RM0400 Table 174. DMA_CERR field descriptions Field Description 0Normal operation 1No operation, ignore bits 1–7 of this register Clear all error indicators 0Clear only those ERR bits specified in the CERR field CAEI 1Clear all bits in ERR 2–7 Clear error indicator CERR...
Page 409: Interrupt Request Register Low (Dma_Intl)
RM0400 Enhanced Direct Memory Access (eDMA) Address: FC0A_0000 + 0x001F Access: User write-only CADN CDNE Reset Figure 130. Clear DONE Status Bit Register (DMA_CDNE) Table 176. DMA_CDNE field descriptions Field Description 0Normal operation 1No operation, ignore bits 1–7 of this register Clears all DONE bits 0Clears only those TCDn_CSR[DONE] bits specified in the CDNE field CADN...
Page 410: Table 177. Dma_Intl Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0400 Address: FC0A_0000 + 0x0024 Access: User read/write Reset W w1c Reset Figure 131. Interrupt Request Register Low (DMA_INTL) Table 177. DMA_INTL field descriptions Field Description Interrupt request 15 0 The interrupt request for corresponding channel is cleared INT15 1 The interrupt request for corresponding channel is active Interrupt request 14...
Page 411: Error Register Low (Dma_Errl)
RM0400 Enhanced Direct Memory Access (eDMA) Table 177. DMA_INTL field descriptions(Continued) Field Description Interrupt request 5 0 The interrupt request for corresponding channel is cleared INT5 1 The interrupt request for corresponding channel is active Interrupt request 4 0 The interrupt request for corresponding channel is cleared INT4 1 The interrupt request for corresponding channel is active Interrupt request 3...
Page 412: Table 178. Dma_Errl Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0400 Address: FC0A_0000 + 0x002C Access: User read/write Reset W w1c Reset Figure 132. Error Register Low (DMA_ERRL) Table 178. DMA_ERRL field descriptions Field Description Error in channel 15 0 An error in the corresponding channel has not occurred ERR15 1 An error in the corresponding channel has occurred Error in channel 14...
Page 413: Hardware Request Status Register Low (Dma_Hrsl)
RM0400 Enhanced Direct Memory Access (eDMA) Table 178. DMA_ERRL field descriptions(Continued) Field Description Error in channel 5 0 An error in the corresponding channel has not occurred ERR5 1 An error in the corresponding channel has occurred Error in channel 4 0 An error in the corresponding channel has not occurred ERR4 1 An error in the corresponding channel has occurred...
Page 414: Table 179. Dma_Hrsl Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0400 Table 179. DMA_HRSL field descriptions Field Description Hardware request status channel 15 0 A hardware service request for the corresponding channel is not present HRS15 1 A hardware service request for the corresponding channel is present Hardware request status channel 14 0 A hardware service request for the corresponding channel is not present HRS14...
Page 415: Channel N Priority Register (Dma_Dchprin)
RM0400 Enhanced Direct Memory Access (eDMA) Table 179. DMA_HRSL field descriptions(Continued) Field Description Hardware request status channel 1 0 A hardware service request for the corresponding channel is not present HRS1 1 A hardware service request for the corresponding channel is present Hardware request status channel 0 0 A hardware service request for the corresponding channel is not present HRS0...
Page 416: Tcd Source Address (Dma_Tcdn_Saddr)
Enhanced Direct Memory Access (eDMA) RM0400 DMA uses the master ID and protection level stored in the DCHMID register instead of the DMA’s default values. When a master (a core, for example) programs a TCD, its master ID and protection level are captured when the TCD Word 7 control attributes are written. Although the scatter/gather operation can change the contents of TCD Word 7, that operation does not affect the DCHMIDn registers.
Page 417: Tcd Transfer Attributes (Dma_Tcdn_Attr)
RM0400 Enhanced Direct Memory Access (eDMA) FC0A_0000h base + 1000h offset + (32d × n), where n = 0d to Address: Access: User read/write SADDR Reset SADDR Reset Figure 136. TCD Source Address (DMA_TCDn_SADDR) 1. x = Undefined at reset. Table 182.
Page 418: Tcd Signed Source Address Offset (Dma_Tcdn_Soff)
Enhanced Direct Memory Access (eDMA) RM0400 Table 183. DMA_TCDn_ATTR field descriptions Field Description Source address modulo. 0 Source address modulo feature is disabled ≠0 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value.
Page 419: Table 185. Dma_Tcdn_Nbytes_Mlno Field Descriptions
RM0400 Enhanced Direct Memory Access (eDMA) 19.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) See TCD Minor Byte Count (Minor Loop Disabled) register figure and DMA_TCDn_NBYTES_MLNO field descriptions table below. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. FC0A_0000h base + 1008h offset + (32d ×...
Page 420 Enhanced Direct Memory Access (eDMA) RM0400 Address: FC0A_0000h base + 1008h offset + (32d × n), where n = 0d to 63d Access: User read/write NBYTES Reset NBYTES Reset Figure 140. TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO) 1.
Page 421: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
RM0400 Enhanced Direct Memory Access (eDMA) Table 186. DMA_TCDn_NBYTES_MLOFFYES field descriptions Field Description Source minor loop offset enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. SMLOE 0 The minor loop offset is not applied to the SADDR 1 The minor loop offset is applied to the SADDR Destination minor loop offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop...
Page 422: Tcd Destination Address (Dma_Tcdn_Daddr)
Enhanced Direct Memory Access (eDMA) RM0400 19.3.25 TCD Destination Address (DMA_TCDn_DADDR) See TCD Destination Address register figure and DMA_TCDn_DADDR field descriptions table as follows. FC0A_0000h base + 1010h offset + (32d × n), where n = 0d to Address: Access: User read/write DADDR Reset DADDR...
Page 423: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
RM0400 Enhanced Direct Memory Access (eDMA) Table 189. DMA_TCDn_CITER_ELINKYES field descriptions Field Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 424: Tcd Signed Destination Address Offset (Dma_Tcdn_Doff)
Enhanced Direct Memory Access (eDMA) RM0400 Table 190. DMA_TCDn_CITER_ELINKNO field descriptions Field Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number.
Page 425: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
RM0400 Enhanced Direct Memory Access (eDMA) 19.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) Address: FC0A_0000h base + 1018h offset + (32d × n), where n = 0d to 63d Access: User read/write DLASTSGA Reset DLASTSGA Reset Figure 147. TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) 1.
Page 426: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
Enhanced Direct Memory Access (eDMA) RM0400 Table 193. DMA_TCDn_BITER_ELINKYES field descriptions Field Description Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 427: Tcd Control And Status (Dma_Tcdn_Csr)
RM0400 Enhanced Direct Memory Access (eDMA) Table 194. DMA_TCDn_BITER_ELINKNO field descriptions Field Description Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
Page 428: Table 195. Dma_Tcdn_Csr Field Descriptions
Enhanced Direct Memory Access (eDMA) RM0400 Table 195. DMA_TCDn_CSR field descriptions Field Description Bandwidth control Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted.
Page 429: Functional Description
RM0400 Enhanced Direct Memory Access (eDMA) Table 195. DMA_TCDn_CSR field descriptions(Continued) Field Description Disable request 0 The channel’s ERQ bit is not affected DREQ 1 The channel’s ERQ bit is cleared when the major loop is complete Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches the halfway point.
Page 430: Edma Basic Data Flow
Enhanced Direct Memory Access (eDMA) RM0400 start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes the new values for the TCDn _{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including updates to the final address pointer, reloading the TCDn _CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
Page 431: Figure 151. Dma Operation, Part 1
RM0400 Enhanced Direct Memory Access (eDMA) memory for TCDn. Next, the TCD memory is accessed and the descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers.
Page 432: Figure 152. Dma Operation, Part 2
Enhanced Direct Memory Access (eDMA) RM0400 Figure 152. DMA operation, part 2 Write Address Write Data Transfer Control Descriptor (TCD) Read Data Read Data Write Data Address eDMA Peripheral eDMA Done Request After the minor byte count has moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs updates to certain fields in the appropriate TCD, for example, SADDR, DADDR, and CITER.
Page 433: Error Reporting And Handling
RM0400 Enhanced Direct Memory Access (eDMA) Figure 153. DMA operation, part 3 Write Address Write Data Transfer Control Descriptor (TCD) e D M A E n g i n e Read Data Read Data Write Data Address eDMA Peripheral eDMA Done Request 19.4.3 Error reporting and handling...
Page 434 Enhanced Direct Memory Access (eDMA) RM0400 All channel priority levels within a group must be unique and all group priority levels among the groups must be unique when Fixed Arbitration mode is enabled. • If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary.
Page 435: Channel Preemption
RM0400 Enhanced Direct Memory Access (eDMA) 19.4.4 Channel preemption Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution.
Page 436 Enhanced Direct Memory Access (eDMA) RM0400 Table 196. eDMA peak transfer rates (Mbyte/s)(Continued) From 32-bit internal From internal SRAM From internal SRAM peripheral bus System speed, width 32-bit internal peripheral internal SRAM internal SRAM 150 MHz, 64 bits 600.0 240.0 240.0 200 MHz, 64 bits 800.0...
Page 437: Table 197. Edma Peak Request Rate (Mreq/S)
RM0400 Enhanced Direct Memory Access (eDMA) For a single SRAM read and two 64-bit internal peripheral bus writes, the combined data phase time is five cycles. • Cycle x + 1: This cycle represents the data phase of the last destination write. •...
Page 438: Initialization/Application Information
Enhanced Direct Memory Access (eDMA) RM0400 For an SRAM to internal peripheral bus transfer, Equation 2 PEAKreq = 150 MHz / [ 4 + (1 + 0) + (1 + 1) + 3 ] cycles = 15.0 Mreq/s For an internal peripheral bus-to-SRAM transfer, Equation 3 PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 0) + 3 ] cycles = 15.0 Mreq/s The minimum number of cycles to perform a single read/write, with zero wait states on the system bus, from a cold start (where no channel is executing and the eDMA is idle):...
Page 439: Table 198. Tcd Control And Status Fields
RM0400 Enhanced Direct Memory Access (eDMA) Table 198. TCD control and status fields TCDn_CSR Description field name Control bit to start channel explicitly when using a software initiated DMA service (automatically START cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution Status bit indicating major loop completion (cleared by software when using a software initiated DONE DMA service)
Page 440: Dma Programming Errors
Enhanced Direct Memory Access (eDMA) RM0400 Figure 155 lists the memory array terms and how the TCD settings interrelate. Figure 155. Memory array terms 19.5.2 DMA programming errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data.
Page 441: Dma Transfer
RM0400 Enhanced Direct Memory Access (eDMA) 19.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. 19.5.4 DMA transfer This section discusses how to perform DMA transfers with the eDMA.
Page 442 Enhanced Direct Memory Access (eDMA) RM0400 User write to the TCDn_CSR[START] bit requests channel service. The channel is selected by arbitration for servicing. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. eDMA engine reads: channel TCD data from local memory to internal register file. The source-to-destination transfers are executed as follows: Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003.
Page 443 RM0400 Enhanced Direct Memory Access (eDMA) First hardware (eDMA peripheral) request for channel service. The channel is selected by arbitration for servicing. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. eDMA engine reads: channel TCDn data from local memory to internal register file. The source to destination transfers are executed as follows: Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003.
Page 444: Edma Tcdn Status Monitoring
Enhanced Direct Memory Access (eDMA) RM0400 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 19.5.4.3 Modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2.
Page 445: Table 201. Tcd Status Sequence – Hardware Activated Channel
RM0400 Enhanced Direct Memory Access (eDMA) Table 200. TCD status sequence – software activated channel(Continued) TCDn_CSR bits Step State START ACTIVE DONE Channel has completed the minor loop and is idle Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware (peripheral) initiated service requests is to read the TCDn_CITER field and test for a change.
Page 446: Channel Linking
Enhanced Direct Memory Access (eDMA) RM0400 simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel. 19.5.6 Channel linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel.
Page 447: Dynamic Programming
RM0400 Enhanced Direct Memory Access (eDMA) Table 202. Channel linking parameters(Continued) Desired link TCD control field name Description behavior CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion Link at end of CSR[MAJOR_LINKCH] major loop Link channel number when linking at end of major loop 19.5.7 Dynamic programming...
Page 448: Table 204. Coherency Model For Method 1
Enhanced Direct Memory Access (eDMA) RM0400 Note: The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 19.5.7.3 Dynamic scatter/gather Dynamic scatter/gather is the process of setting the TCD.e_sg bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution.
Page 449: Table 205. Coherency Model For Method 2
RM0400 Enhanced Direct Memory Access (eDMA) Table 204. Coherency model for method 1(Continued) Step Action Read back the 16 bit TCD control/status field. Test the TCD.e_sg request status and TCD.major.linkch value: – If e_sg = 1b, the dynamic link attempt was successful. –...
Page 450: Direct Memory Access Multiplexer (Dmamux)
Direct Memory Access Multiplexer (DMAMUX) RM0400 Direct Memory Access Multiplexer (DMAMUX) 20.1 Introduction Note: For the chip-specific implementation details of this module’s instances, see the chip configuration information. 20.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels.
Page 451: Features
RM0400 Direct Memory Access Multiplexer (DMAMUX) 20.1.2 Features The DMAMUX module provides these features: • Up to 64 peripheral slots and up to six always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. – The first eight channels additionally provide a trigger functionality.
Page 452: Channel Configuration Register (Dmamux_Chcfgn)
Direct Memory Access Multiplexer (DMAMUX) RM0400 Table 206. DMAMUX memory map(Continued) Absolute Width Reset Section/ address Register name Access (in bits) value page (hex) Channel Configuration register (DMAMUX_CHCFG5) 20.3.1/452 Channel Configuration register (DMAMUX_CHCFG6) 20.3.1/452 Channel Configuration register (DMAMUX_CHCFG7) 20.3.1/452 Channel Configuration register (DMAMUX_CHCFG8) 20.3.1/452 Channel Configuration register (DMAMUX_CHCFG9) 20.3.1/452...
Page 453: Functional Description
RM0400 Direct Memory Access Multiplexer (DMAMUX) Table 207. DMAMUX_CHCFGn field descriptions Field Description DMA Channel Enable. Enables the DMA channel 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMUX. The ENBL DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
Page 454: Figure 158. Dmamux Triggered Channels
Direct Memory Access Multiplexer (DMAMUX) RM0400 Figure 158. DMAMUX triggered channels Source #1 Source #2 Source #3 DMA channel #0 Trigger #1 Source #x DMA channel #m-1 Trigger #m Always #1 Always #y The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 455: Dma Channels With No Triggering Capability
RM0400 Direct Memory Access Multiplexer (DMAMUX) Figure 160. DMAMUX channel triggering: ignored trigger Periph request Trigger DMA request This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •...
Page 456: Initialization/Application Information
Direct Memory Access Multiplexer (DMAMUX) RM0400 enabled provide no such "throttling" of the data transfers. These sources are most useful in the following cases: • Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA triggering capability).
Page 457 RM0400 Direct Memory Access Multiplexer (DMAMUX) Determine with which DMA channel the source will be associated. Note that only the first DMA channels have periodic triggering capability. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
Page 458 Direct Memory Access Multiplexer (DMAMUX) RM0400 In File main.c: #include "registers.h" *CHCFG1 = 0x00; *CHCFG1 = 0xC5; To enable a source without periodic triggering: Determine with which DMA channel the source will be associated. Note that only the first DMA channels have periodic triggering capability. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
Page 459 RM0400 Direct Memory Access Multiplexer (DMAMUX) volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);...
Page 460 Direct Memory Access Multiplexer (DMAMUX) RM0400 volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);...
Page 461: Clocking
RM0400 Clocking Clocking 21.1 Introduction This chapter describes the architecture for the system level clocks and includes the following information: • System clock specifics • Clock architecture • Clock sources • Clock monitoring • Programmable clock dividers • Clock control registers •...
Page 462: Figure 161. Clock Generation
Clocking RM0400 Figure 161. Clock generation Note: All dividers shown in the diagram are integer dividers with a range of 1, 2, 3,.., n. FCD are fractional clock dividers. All clock dividers are 50% duty cycle. XOSC CORE_CLK (Core) ÷ 1…64 XBAR_CLK (XBAR) 8 –...
Page 463: Mc_Cgm Registers
RM0400 Clocking 21.2.1 MC_CGM registers Table 208 shows the relationship between the clocks in Figure 161 and the MC_CGM registers. Table 208. MC_CGM relationship to clocks MC_CGM register(s) Register description Output clock Core (CORE_CLK), XBAR CGM_SC_DC0 System Clock Divider Configuration 0 (XBAR_CLK) CGM_SC_DC1 System Clock Divider Configuration 1...
Page 464: Jtag Frequencies
Clocking RM0400 Table 209. Maximum system level clock frequencies (Continued) System clock Max frequency (MHz) PBRIDGE_A GTM slot Interrupt controller DSPI_CLK, LIN_CLK Peripheral clock ADCs 14.6 Ethernet FEC_REF_CLK, TXCLK, RXCLK 50, 25, 25 1. The user is responsible to verify that these values are not exceeded. 2.
Page 465: Clock Sources
RM0400 Clocking 21.5 Clock sources The following clock sources are described in this section: • PLL0 • External oscillator (XOSC) • External clock (EXTAL bypass) • 16 MHz internal RC oscillator (IRCOSC) 21.5.1 The PLL provides separate system and peripheral clocks as shown in Figure 161.
Page 466: Table 211. Pll Register Write Protection
Clocking RM0400 Table 211. PLL register write protection Offset Register Protection PLL0 Control Register (PLL0CR) PLL0 Status Register (PLL0SR) PLL0 Divider Register (PLL0DIVR) 1. See Register Protection Configuration chapter for bit field details. 21.5.1.2 PLL register reset values The reset values for the device-specific PLLDIG registers are shown in Table 212.
Page 467: External Oscillator (Xosc)
RM0400 Clocking should be used to make sure the mode transition completes. Mode transition will NOT complete until: – XOSC counter expires (if the new mode configuration changes MC_ME_<mode>_MC[XOSCON] = 1), and – PLL is locked (if the new mode configuration changes MC_ME_<mode>_MC[PLLON] = 1) Confirm the desired target mode was entered by checking the status of MC_ME_GS[S_CURRENT_MODE].
Page 468: Mhz Internal Rc Oscillator (Ircosc)
Clocking RM0400 reset value for the XOSC trimming capacitors does not trim the internal capacitor values (UTEST Misc bit 5:1 = 00000b (XOSC LOAD CAP SEL)). The internal load capacitor values stored in UTEST flash memory row have triple-voting flip- flop (TVF) implementation to prevent an incorrect value, and thus an undetectable error in the system.
Page 469: Peripheral Clocks
RM0400 Clocking 21.5.3.2 IRCOSC reset value Table 215 shows the default reset value for the IRCOSC registers. The values of the IRCOSC registers are loaded from TEST DCF flash memory (16 MHz RCOSC_1, 16 MHz RCOSC_2, 16 MHz RCOSC_3, 16 MHz RCOSC_4) (see Device Configuration Format Records chapter for details).
Page 470: Lfast Clocking
Clocking RM0400 Figure 163. Clock distribution sys_clk aei_clock (BIU) XBAR_CLK Ext. Modulator Clock SD_CLK SDADC SDADC Digital I/F (1) Module Clock SENT (1) Protocol Clock SENT_CLK SAR_CLK LIN_CLK Module Clock SARADC Digital I/F (3) LINFlexD (3) DSPI1_CLK Module Clock Module Clock DSPI_0 Decimation Unit...
Page 471: Table 216. Lfast And Ethernet Use Cases
RM0400 Clocking If SPC572Lx is operated as LFAST slave the reference clock coming from the LFAST master is fed as an external clock signal (EXTAL bypass) to be used by the PLL0 as clock input. If SPC572Lx is operated as LFAST master the reference clock is selectable by “AUX Clock Selector 1”...
Page 472: Ethernet Clocking
Clocking RM0400 21.6.2 Ethernet clocking Both internal and external clocks sources for RMII Ethernet interface mode are supported. The RMII clock (FEC_REF_CLK) is 50 MHz. Figure 165 gives the connections for the Ethernet clocks. The FEC_REF_CLK can be generated internally or input to the device. FEC_REF_CLK can be generated internally and fed to both the PHY device and to the RMII gasket by enabling the FEC_REF_CLK pad input and output buffers.
Page 473: Sigma-Delta Adc Clocking
RM0400 Clocking 21.6.4 Sigma-Delta ADC clocking The analog portion of the Sigma-Delta ADC (SDADC) works with either an internal or external modulator. The internal clock (SD_CLK, see Figure 163) is always used when the internal modulator in the SDADC is enabled. This device supports either an external input clock (BS_CK), or internally generated output clock (SD_CLK) when using an external modulator.
Page 474: Clock Monitoring
Clocking RM0400 There are two GTM output clocks available on package pins, EXTCLK[2:1]. EXTCLK[1] is muxed on the same pins as SYSCLK[1]. EXTCLK[2] is muxed on the same pin as the Ethernet RMII clock (FEC_REF_CLK). The selection of EXTCLK[n], SYSCLK[n] or FEC_REF_CLK is done in the SIUL2_MSCR registers and shown in Figure 167.
Page 475: Table 217. Clock Input Sources
RM0400 Clocking Figure 168. CMU0 block diagram CMU_CSR[CKSEL1] CMU_MDR CLK_SEL CLKMT0_RMN (IRCOSC) 00,11 CMU_FDR Frequency Meter CLKMN0_RMT (XOSC) CLKMN0_RMT Supervisor RCDIV < f CLKMN0_RMT CLKMT0_RMN (from MC_ME) CLKMN0_RMT_ACTIVE CLKMN1 Supervisor CMU_HREF Fixed Prescaler > hfref CLKMN1 CLKMN1 (monitored clock) < lfref CLKMN1 CMU_LFREF CLKMN1_ACTIVE...
Page 476: Pll0 Monitor
Clocking RM0400 Table 218. CMU registers availability Address offset Register 0000h CMU_CSR CMU0 0004h CMU_FDR CMU0 0008h CMU_HFREFR CMU0 000Ch CMU_LFREFR CMU0 0010h CMU_ISR CMU0 0014h Reserved — 0018h CMU_MDR CMU0 21.7.1.3 CMU register write protection The CMU registers have write protection as shown in Table 219.
Page 477: Loss Of System Clock Behavior
RM0400 Clocking 21.8 Loss of system clock behavior This device has built-in mechanisms for detecting loss of the oscillator or PLL clocks, and provides several options for reaction to a loss of clock in the application. Figure 169 gives a high-level view of the loss of clock logic.
Page 478: Pll Digital Interface (Plldig)
PLL Digital Interface (PLLDIG) RM0400 PLL Digital Interface (PLLDIG) 22.1 Introduction The MCU provides a user interface and control over the PLL system (PLLDIG). 22.2 Block Diagram The block diagram of the PLLDIG block is found in the “Clocking chapter” of the SPC572Lx Reference Manual.
Page 479: Memory Map And Register Definition
RM0400 PLL Digital Interface (PLLDIG) 22.5 Memory map and register definition This section provides the memory map and detailed descriptions of all registers for configuring the PLLs. 22.5.1 Memory map Table 220 shows the memory map. Addresses are given as offsets from the module base address.
Page 480: Table 221. Pllcr Field Descriptions
PLL Digital Interface (PLLDIG) RM0400 22.5.2.1 PLL Control Register (PLLCR) Offset: 0000h Access: User read/write Reset <Cr CLKCFG oss Refs>2 Reset This field can be written at any time, but writes are ignored. Reads returns previously written value. CLKCFG can be written, but writes have no effect. Mode changes are implemented by writing to the appropriate MC_ME_<mode>_MC register (see the "Mode Entry Module (MC_ME)"...
Page 481: Table 222. Pllsr Field Descriptions
RM0400 PLL Digital Interface (PLLDIG) Table 221. PLLCR field descriptions(Continued) Field Description Loss of lock reset enable. The PLLCR[LOLRE] bit determines whether system reset is asserted or not upon a loss of lock indication from PLL. If both PLL0CR[LOLRE] = 1 and PLL0CR[LOLIE] = 1, PLL0CR[LOLRE] has precedence and the device asserts reset with the interrupt not being taken.
Page 482: Table 223. Plldv Field Descriptions
PLL Digital Interface (PLLDIG) RM0400 Table 222. PLLSR field descriptions(Continued) Field Description Lock status bit. Indicates whether PLL has acquired lock. 0 PLL is unlocked. LOCK 1 PLL is locked. Reserved Reserved 22.5.2.3 PLL Divider Register (PLLDV) The PLLDV register provides the PHI/PHI1 output clock reduced frequency dividers, pre- divider, and loop divider.
Page 483: Register Classification For Safety Requirements
RM0400 PLL Digital Interface (PLLDIG) Table 223. PLLDV field descriptions(Continued) Field Description PHI reduced frequency divider. This 6-bit field determines the VCO clock post divider for driving the PHI output clock. 00 Reserved 01 Divide by 1 10:15 02 Divide by 2 RFDPHI 03 Divide by 3 ..
Page 484: Clock Configuration
PLL Digital Interface (PLLDIG) RM0400 22.6.2 Clock configuration The relationship between input and output frequency is determined by programming the PLLDV register, and calculated according to the following equations: Equation 4 PLLDV MFD × --------------------------------------------------------------------------------------------------------- f pll_phi f pll_ref ] PLLDV RFDPHI ×...
Page 485: Loss Of Lock
RM0400 PLL Digital Interface (PLLDIG) 22.6.3 Loss of lock The PLL digital interface registers provide the flexibility to select whether to generate an interrupt assert system reset or do nothing in the event that the PLL loses lock according to the available PLLnCR options.
Page 486: Clock Monitor Unit (Cmu)
Clock Monitor Unit (CMU) RM0400 Clock Monitor Unit (CMU) 23.1 Introduction The Clock Monitor Unit (CMU), also referred to as Clock Quality Checker or Clock Fault Detector, serves three purposes: • Measures the frequency of clock sources CLKMT0_RMN with CLKMN0_RMT as the reference clock •...
Page 487: Signals
RM0400 Clock Monitor Unit (CMU) Figure 173. Clock Monitor Unit diagram CMU_CSR[CKSEL1] *Not used in all CMU block CMU_MDR configurations. See the “Clocking” CLKMT1 CLK_SEL chapter for specific CMU CLKMT2 implementations. 00,11 CMU_FDR Frequency Meter CLKMN0_RMT (XOSC) CLKMN0_RMT Supervisor RCDIV <...
Page 488: Memory Map And Register Definition
Clock Monitor Unit (CMU) RM0400 23.4 Memory map and register definition This section describes in address order all the CMU registers. Each description includes a standard register diagram with an associated figure number. The CMU memory map is listed in Table 225.
Page 489: Table 226. Cmu_Csr Field Descriptions
RM0400 Clock Monitor Unit (CMU) Table 226. CMU_CSR field descriptions Field Description Reserved Start frequency measure. The software can only set this bit to start a clock frequency measure. It is reset by hardware when the measure is ready in the CMU_FDR. 0 Frequency measurement is completed or not yet started 1 Frequency measurement is not completed 9:21...
Page 490: Table 227. Cmu_Fdr Field Descriptions
Clock Monitor Unit (CMU) RM0400 Table 227. CMU_FDR field descriptions Field Description 0:11 Reserved Measured frequency bits. This register displays the measured frequency (f ) with respect to the 12:31 reference clock (f ). The measured value is given by the following formula: CLKMN0_RMT = (f ×...
Page 491: Table 229. Cmu_Lfrefr Field Descriptions
RM0400 Clock Monitor Unit (CMU) Address: Base + 000Ch Access: User read/write Reset LFREF Reset Figure 177. CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR) Table 229. CMU_LFREFR field descriptions Field Description 0:19 Reserved 20:31 Low Frequency reference value. These bits determine the low reference value for the LFREF CLKMN1 frequency.
Page 492: Table 230. Cmu_Isr Field Descriptions
Clock Monitor Unit (CMU) RM0400 Table 230. CMU_ISR field descriptions Field Description 0:28 Reserved CLKMN1 frequency higher than high reference event status. This bit is set by hardware when CLKMN1 frequency becomes higher than HFREF value and CLKMN1 is ‘ON’ as signaled by the MC_ME.
Page 493: Functional Description
RM0400 Clock Monitor Unit (CMU) Table 231. CMU_MDR field descriptions Field Description 0:11 Reserved Measurement duration bits. This field displays the measurement duration in terms of selected 12:31 clock (CLKMT0_RMN) cycles. This value is loaded in the frequency meter down-counter. The down-counter starts counting when CMU_CSR [SFM] = 1. 23.5 Functional description This section describes the functionality of the CMU.
Page 494 Clock Monitor Unit (CMU) RM0400 Note: An example of determining the HFREF value is as follows. Assume a Actual = 16 MHz with an accuracy of +/-5%. In order to monitor f = 200 MHz, CLKMT0_RMN CLKMN1 the ideal HFREF = 800.
Page 495: Clock Generation Module (Mc_Cgm)
RM0400 Clock Generation Module (MC_CGM) Clock Generation Module (MC_CGM) 24.1 Introduction 24.1.1 Overview The clock generation module (MC_CGM) generates reference clocks for all the chip blocks. The MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock selection (see the MC_ME chapter for more details).
Page 496: Figure 180. Mc_Cgmblock Diagram
Clock Generation Module (MC_CGM) RM0400 Figure 180. MC_CGMblock diagram MC_CGM MC_ME XOSC Registers Platform Interface MC_RGM PLL0 System Clock Peripherals Multiplexer/Divider Auxiliary Clock Selector/Divider SYSCLK1 Core Mapped peripherals 496/2058 DocID027809 Rev 4...
Page 497: Features
RM0400 Clock Generation Module (MC_CGM) 24.1.2 Features The MC_CGM includes the following features: • generates system and peripheral clocks • selects and enables/disables the system clock supply from system clock sources according to MC_ME control • performs progressive system clock frequency change depending on MC_ME mode configuration •...
Page 498 Clock Generation Module (MC_CGM) RM0400 Table 232. MC_CGM register description(Continued) Offset Access (Base Name Size Location 0xFFFB_ User Supervisor Test 0700) PCS Divider End for PLL0 PHI1 Register 0x0024 word read read/write read/write on page 505 (CGM_PCS_DIVE3) System Clock Select Status Register 0x00E4 word read...
Page 499: Register Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 232. MC_CGM register description(Continued) Offset Access (Base Name Size Location 0xFFFB_ User Supervisor Test 0700) Aux Clock 8 Divider Configuration 0 0x0208 word read read/write read/write on page 522 Register (CGM_AC8_DC0) Aux Clock 10 Select Control Register 0x0240 word read...
Page 500: Table 233. Pcs Switch Duration Register (Cgm_Pcs_Sdur) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 233. PCS Switch Duration Register (CGM_PCS_SDUR) field descriptions Field Description 0–7 Switch Duration — This value defines the duration of one PCS clock switch step in terms of 16 MHz internal RC oscillator (IRCOSC) cycles. SDUR 24.3.1.2 PCS Divider Change Register 1 (CGM_PCS_DIVC1)
Page 501: Table 235. Pcs Divider Start Register 1 (Cgm_Pcs_Divs1) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Address 0x0708 Access: User read/write, Supervisor read/write, Test read DIVS[19:16] Reset DIVS[15:0] Reset Figure 183. PCS Divider Start Register 1 (CGM_PCS_DIVS1) Table 235. PCS Divider Start Register 1 (CGM_PCS_DIVS1) field descriptions Field Description 0–11 Reserved 12–31 Divider Start Value —...
Page 502: Table 237. Pcs Divider Change Register 2 (Cgm_Pcs_Divc2) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 24.3.1.5 PCS Divider Change Register 2 (CGM_PCS_DIVC2) This register defines the rate of frequency change and initial change value for the progressive system clock switching when switching the system clock source to or from the PLL0 PHI on ramp-up and ramp- down, respectively.
Page 503: Table 238. Pcs Divider Start Register 2 (Cgm_Pcs_Divs2) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Address 0x0714 Access: User read/write, Supervisor read/write, Test read DIVS[19:16] Reset DIVS[15:0] Reset Figure 186. PCS Divider Start Register 2 (CGM_PCS_DIVS2) Table 238. PCS Divider Start Register 2 (CGM_PCS_DIVS2) field descriptions Field Description 0–11 Reserved 12–31 Divider Start Value —...
Page 504: Table 240. Pcs Divider Change Register 3 (Cgm_Pcs_Divc3) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 24.3.1.8 PCS Divider Change Register 3 (CGM_PCS_DIVC3) This register defines the rate of frequency change and initial change value for the progressive system clock switching when switching the system clock source to or from the PLL0 PHI1 on ramp-up and ramp- down, respectively.
Page 505: Table 241. Pcs Divider Start Register 3 (Cgm_Pcs_Divs3) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Address 0x0720 Access: User read/write, Supervisor read/write, Test read DIVS[19:16] Reset DIVS[15:0] Reset Figure 189. PCS Divider Start Register 3 (CGM_PCS_DIVS3) Table 241. PCS Divider Start Register 3 (CGM_PCS_DIVS3) field descriptions Field Description 0–11 Reserved 12–31 Divider Start Value —...
Page 506: Table 243. System Clock Select Status Register (Cgm_Sc_Ss) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 24.3.1.11 System Clock Select Status Register (CGM_SC_SS) This register provides the current system clock source selection. Address 0x07E4 Access: User read, Supervisor read, Test read SELSTAT SWTRG SWIP Reset Reset Figure 191. System Clock Select Status Register (CGM_SC_SS) Table 243.
Page 507: Table 244. System Clock Divider 0 Configuration Register (Cgm_Sc_Dc0) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 243. System Clock Select Status Register (CGM_SC_SS) field descriptions(Continued) Field Description Switch In Progress 0 clock source switching has completed SWIP 1 clock source switching is in progress 16–31 Reserved 24.3.1.12 System Clock Divider 0 Configuration Register (CGM_SC_DC0) This register controls system clock divider 0.
Page 508: Table 245. System Clock Divider 1 Configuration Register (Cgm_Sc_Dc1) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Address 0x07EC Access: User read/write, Supervisor read/write, Test read/write R DE Reset Reset Figure 193. System Clock Divider 1 Configuration Register (CGM_SC_DC1) Table 245. System Clock Divider 1 Configuration Register (CGM_SC_DC1) field descriptions Field Description Divider 1 Enable —...
Page 509: Table 246. Auxiliary Clock 0 Select Control Register (Cgm_Ac0_Sc) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 246. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 0 Source Selection Control — Selects the source for auxiliary clock 0. 0000 IRCOSC 0001 XOSC 0010 PLL0 PHI 0011 reserved 0100 reserved 0101 reserved...
Page 510: Table 247. Auxiliary Clock 0 Select Control Register (Cgm_Ac0_Sc) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 247. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 0 Source Selection Status — This value indicates the current source for auxiliary clock 0. 0000 IRCOSC 0001 XOSC 0010 PLL0 PHI 0011 reserved 0100 reserved...
Page 511: Table 249. Auxiliary Clock 0 Divider 1 Configuration Register (Cgm_Ac0_Dc1) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 248. Auxiliary Clock 0 Divider 0 Configuration Register (CGM_AC0_DC0) field descriptions(Continued) Field Description Divider Division Value — The resultant peripheral clock will have a period ‘DIV + 1’ times that of auxiliary 12–15 clock 0. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the peripheral clock remains disabled.
Page 512: Table 250. Auxiliary Clock 0 Divider 2 Configuration Register (Cgm_Ac0_Dc2) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Address 0x0810 Access: User read/write, Supervisor read/write, Test read/write Reset Reset Figure 198. Auxiliary Clock 0 Divider 2 Configuration Register (CGM_AC0_DC2) Table 250. Auxiliary Clock 0 Divider 2 Configuration Register (CGM_AC0_DC2) field descriptions Field Description Divider Enable 0 Disable auxiliary clock 0 divider 2 1 Enable auxiliary clock 0 divider 2...
Page 513: Table 251. Auxiliary Clock 1 Select Control Register (Cgm_Ac1_Sc) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 251. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock 0000 reserved 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 514: Table 252. Auxiliary Clock 1 Select Status Register (Cgm_Ac1_Ss) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 252. Auxiliary Clock 1 Select Status Register (CGM_AC1_SS) field descriptions Field Description 0–3 Reserved Auxiliary Clock 1 Source Selection Status — This value indicates the current source for auxiliary clock 1. 0000 reserved 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 515: Table 254. Auxiliary Clock 2 Divider 0 Configuration Register (Cgm_Ac2_Dc0) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 253. Auxiliary Clock 1 Divider 0 Configuration Register (CGM_AC1_DC0) field descriptions(Continued) Field Description Divider Division Value — The resultant LFAST clock will have a period ‘DIV + 1’ times that of auxiliary 9–15 clock 1. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the LFAST clock remains disabled.
Page 516: Table 255. Auxiliary Clock 3 Select Control Register (Cgm_Ac3_Sc) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Address 0x0860 Access: User read/write, Supervisor read/write, Test read/write SELCTL Reset Reset Figure 203. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) Table 255. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 3 Source Selection Control —...
Page 517: Table 256. Auxiliary Clock 3 Select Status Register (Cgm_Ac3_Ss) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Address 0x0864 Access: User read, Supervisor read, Test read SELSTAT Reset Reset Figure 204. Auxiliary Clock 3 Select Status Register (CGM_AC3_SS) Table 256. Auxiliary Clock 3 Select Status Register (CGM_AC3_SS) field descriptions Field Description 0–3 Reserved Auxiliary Clock 3 Source Selection Status —...
Page 518: Table 257. Auxiliary Clock 7 Select Control Register (Cgm_Ac7_Sc) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 24.3.1.25 Auxiliary Clock 7 Select Control Register (CGM_AC7_SC) Address 0x08E0 Access: User read/write, Supervisor read/write, Test read/write SELCTL Reset Reset Figure 205. Auxiliary Clock 7 Select Control Register (CGM_AC7_SC) This register is used to select the current clock source for the following clocks: •...
Page 519: Table 258. Auxiliary Clock 7 Select Status Register (Cgm_Ac7_Ss) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) 24.3.1.26 Auxiliary Clock 7 Select Status Register (CGM_AC7_SS) Address 0x08E4 Access: User read, Supervisor read, Test read SELSTAT Reset Reset Figure 206. Auxiliary Clock 7 Select Status Register (CGM_AC7_SS) This register provides the current auxiliary clock 7 source selection. Table 258.
Page 520: Table 259. Auxiliary Clock 7 Divider 0 Configuration Register (Cgm_Ac7_Dc0) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 24.3.1.27 Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0) Address 0x08E8 Access: User read/write, Supervisor read/write, Test read/write Reset Reset Figure 207. Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0) This register controls auxiliary clock 7 divider 0. Note: Byte and half-word write accesses are not allowed for this register.
Page 521: Table 260. Auxiliary Clock 8 Select Control Register (Cgm_Ac8_Sc) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Figure 225 for details. Table 260. Auxiliary Clock 8 Select Control Register (CGM_AC8_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 8 Source Selection Control — This value selects the current source for auxiliary clock 0000 reserved 0001 XOSC 0010 PLL0 PHI...
Page 522: Table 261. Auxiliary Clock 8 Select Status Register (Cgm_Ac8_Ss) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 261. Auxiliary Clock 8 Select Status Register (CGM_AC8_SS) field descriptions Field Description 0–3 Reserved Auxiliary Clock 8 Source Selection Status — This value indicates the current source for auxiliary clock 8. 0000 reserved 0001 XOSC 0010 PLL0 PHI 0011 reserved 0100 reserved...
Page 523: Table 262. Auxiliary Clock 8 Divider 0 Configuration Register (Cgm_Ac8_Dc0) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 262. Auxiliary Clock 8 Divider 0 Configuration Register (CGM_AC8_DC0) field descriptions Field Description Divider Enable 0 Disable auxiliary clock 8 divider 0 1 Enable auxiliary clock 8 divider 0 1–9 Reserved Divider Division Value — The resultant CCCU clock will have a period ‘DIV + 1’ times that of auxiliary clock 10–15 8.
Page 524: Table 263. Auxiliary Clock 10 Select Control Register (Cgm_Ac10_Sc) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 263. Auxiliary Clock 10 Select Control Register (CGM_AC10_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 10 Source Selection Control — This value selects the current source for auxiliary clock 0000 reserved 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 525: Table 264. Auxiliary Clock 10 Select Status Register (Cgm_Ac10_Ss) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 264. Auxiliary Clock 10 Select Status Register (CGM_AC10_SS) field descriptions Field Description 0–3 Reserved Auxiliary Clock 10 Source Selection Status — This value indicates the current source for auxiliary clock 10. 0000 reserved 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 526: Figure 214. Auxiliary Clock 11 Select Control Register (Cgm_Ac11_Sc)
Clock Generation Module (MC_CGM) RM0400 Table 265. Auxiliary Clock 10 Divider 0 Configuration Register (CGM_AC10_DC0) field descriptions Field Description Divider Enable 0 Disable auxiliary clock 10 divider 0 1 Enable auxiliary clock 10 divider 0 1–11 Reserved Divider Division Value — The resultant FEC reference clock will have a period ‘DIV + 1’ times that of 12–15 auxiliary clock 10.
Page 527: Table 266. Auxiliary Clock 11 Select Control Register (Cgm_Ac11_Sc) Field Descriptions
RM0400 Clock Generation Module (MC_CGM) Table 266. Auxiliary Clock 11 Select Control Register (CGM_AC11_SC) field descriptions Field Description 0–3 Reserved Auxiliary Clock 11 Source Selection Control — This value selects the current source for auxiliary clock 0000 IRCOSC 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 528: Table 267. Auxiliary Clock 11 Select Status Register (Cgm_Ac11_Ss) Field Descriptions
Clock Generation Module (MC_CGM) RM0400 Table 267. Auxiliary Clock 11 Select Status Register (CGM_AC11_SS) field descriptions Field Description 0–3 Reserved Auxiliary Clock 11 Source Selection Status — This value indicates the current source for auxiliary clock 11. 0000 IRCOSC 0001 XOSC 0010 PLL0 PHI 0011 PLL0 PHI1 0100 reserved...
Page 529: Figure 217. Auxiliary Clock 11 Divider 1 Configuration Register (Cgm_Ac11_Dc1)
RM0400 Clock Generation Module (MC_CGM) Table 268. Auxiliary Clock 11 Divider 0 Configuration Register (CGM_AC11_DC0) field descriptions Field Description Divider Enable 0 Disable auxiliary clock 11 divider 0 1 Enable auxiliary clock 11 divider 0 1–2 Reserved Divider Division Value — The resultant DSPI clock 0 will have a period ‘DIV + 1’ times that of auxiliary 3–15 clock 11.
Page 530: Functional Description
Clock Generation Module (MC_CGM) RM0400 Table 269. Auxiliary Clock 11 Divider 1 Configuration Register (CGM_AC11_DC1) field descriptions(Continued) Field Description Divider Division Value — The resultant DSPI clock 1 will have a period ‘DIV + 1’ times that of auxiliary 12–15 clock 11.
Page 531: Table 270. Mc_Cgm Cgm_Pcs_Divcn[Rate] Values
RM0400 Clock Generation Module (MC_CGM) 24.4.1.2.3 Configuration of CGM_PCS_DIVCn[RATE] For a given maximum allowed frequency change rate a the value d to be programmed into the PCS_DIVCn[RATE] r Table 270 egister is given in Table 270. MC_CGM CGM_PCS_DIVCn[RATE] values d = CGM_PCS_DIVCn[RATE] 0.05 0.012 0.10...
Page 532: Figure 218. Mc_Cgm System Clock Ramp-Down Timing (K = 6 Example)
Clock Generation Module (MC_CGM) RM0400 Figure 218. MC_CGM System Clock Ramp-Down Timing (k = 6 example) curr ≤ a × f curr CGM_PCS_SDUR ÷ PCS_DIVEn[DIVE] curr 16MHz steps busy 24.4.1.2.6 Clock Ramp-Up The clock ramp-up starts with the given divider value PCS_DIVSn[DIVS] and with the given divider decrement value PCD_DIVCn[INIT] and ends with the divider value 1.
Page 533: Tion
RM0400 Clock Generation Module (MC_CGM) Figure 219. MC_CGM System Clock Ramp-Up Timing (k = 6 example) targ CGM_PCS_SDUR ≤ a × f targ 16MHz ÷ PCS_DIVSn[DIVS] targ steps busy 24.4.1.3 System Clock Disable During the TEST mode, the system clock can be disabled by the MC_ME. 24.4.1.4 System Clock Dividers The MC_CGM generates the following derived clocks from the system clock:...
Page 534: Tion
Clock Generation Module (MC_CGM) RM0400 In this case, system clock divider 1 has a division factor greater than that of system clock divider 0. Since 2 is an integer multiple of 1, its configration is correct. Also, system clock divider 3 has a division factor that is greater than those of both system clock dividers 0 and 1.
Page 535: Auxiliary Clock Generation
RM0400 Clock Generation Module (MC_CGM) 24.4.2 Auxiliary Clock Generation Figure 220 through Figure 226 show the block diagrams of the generation logic for the various auxiliary clocks. See the following sections for auxiliary clock selection control: • Section 24.3.1.14: Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) •...
Page 536: Figure 221. Mc_Cgm Auxiliary Clock 1 Generation Overview
Clock Generation Module (MC_CGM) RM0400 Figure 221. MC_CGM Auxiliary Clock 1 Generation Overview XOSC PLL0 PHI PLL0 PHI1 (unused) CGM_AC1_DC0 Register LFAST clock clock divider CGM_AC1_SC Register Figure 222. MC_CGM Auxiliary Clock 2 Generation Overview CGM_AC2_DC0 Register PLL0 PHI SENT clock divider 536/2058 DocID027809 Rev 4...
Page 537: Figure 223. Mc_Cgm Auxiliary Clock 3 Generation Overview
RM0400 Clock Generation Module (MC_CGM) Figure 223. MC_CGM Auxiliary Clock 3 Generation Overview IRCOSC XOSC PLL0 reference clock CGM_AC3_SC Register Figure 224. MC_CGM Auxiliary Clock 7 Generation Overview IRCOSC XOSC PLL0 PHI PLL0 PHI1 (unused) CGM_AC7_DC0 Register SYSCLK1 pin clock clock divider CGM_AC7_SC Register DocID027809 Rev 4...
Page 538: Figure 225. Mc_Cgm Auxiliary Clock 8 Generation Overview
Clock Generation Module (MC_CGM) RM0400 Figure 225. MC_CGM Auxiliary Clock 8 Generation Overview XOSC PLL0 PHI (unused) CGM_AC8_DC0 Register jitter enable from PASS clock divider CCCU clock CGM_AC8_SC Register Figure 226. MC_CGM Auxiliary Clock 10 Generation Overview XOSC PLL0 PHI PLL0 PHI1 (unused) CGM_AC10_DC0 Register...
Page 539: Figure 227. Mc_Cgm Auxiliary Clock 11 Generation Overview
RM0400 Clock Generation Module (MC_CGM) Figure 227. MC_CGM Auxiliary Clock 11 Generation Overview IRCOSC XOSC PLL0 PHI PLL0 PHI1 (unused) CGM_AC11_DC0 Register DSPI clock 0 clock divider CGM_AC11_DC1 Register CGM_AC11_SC Register DSPI clock 1 clock divider 24.4.2.1 Auxiliary Clock Dividers The MC_CGM generates the following derived clocks: •...
Page 540: Dividers Functional Description
Clock Generation Module (MC_CGM) RM0400 24.4.3 Dividers Functional Description Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the following control registers for built-in dividers: • Section 24.3.1.12, System Clock Divider 0 Configuration Register (CGM_SC_DC0) •...
Page 541: Figure 228. Mc_Cgm Fractional Division Example Waveform (Divide By 2.3)
RM0400 Clock Generation Module (MC_CGM) Figure 228. MC_CGM Fractional Division Example Waveform (divide by 2.3) source clock ideal divided clock rsing edge -20% +20% -10% +10% -20% +20% -10% +10% -20% deviation actual divided clock local division factor Equation 14 ÷...
Page 542: Osc Digital Interface (Xosc)
OSC Digital Interface (XOSC) RM0400 OSC Digital Interface (XOSC) 25.1 Introduction The XOSC digital interface is used to control the on-chip oscillator (XOSC) and provide the register interface for the programmable features. Selection of the XOSC as a source clock is controlled by the Clock Generation module (MC_CGM).
Page 543: Oscillator Startup Delay
RM0400 OSC Digital Interface (XOSC) 25.2.2 Oscillator startup delay A bit in the UTEST flash memory determines whether the analog portion of the oscillator is enabled at powerup. If enabled, the analog portion of the oscillator is powered-up during Phase3 of the device reset sequence (pre-self-test sequence). In order to allow the oscillator to reach full amplitude before use, the internal counter (OSCCNT) is started when the device exits reset.
Page 544: Register Descriptions
OSC Digital Interface (XOSC) RM0400 Table 274. XOSC memory map Offset Register Location XOSC_CTL—XOSC Control Register Section 25.3.1.1 25.3.1 Register descriptions 25.3.1.1 XOSC control register (XOSC_CTL) Offset 00h Access: Read/Write EOCV Reset – – – – – – – – –...
Page 545 RM0400 OSC Digital Interface (XOSC) Table 275. XOSC_CTL register field descriptions(Continued) Field Description Crystal oscillator clock interrupt. This bit can only be set by hardware when OSCCNT counter reaches the count value EOCV × 512. It is cleared by software by writing 1. I_OSC 0 No oscillator clock interrupt occurred.
Page 546: Ircosc Digital Interface
IRCOSC digital interface RM0400 IRCOSC digital interface 26.1 Introduction The Internal RC Oscillator digital interface (IRCOSC) controls the internal 16 MHz RC oscillator system. This oscillator system includes the main internal RC oscillator (MRC), as well as an internal temperature sensor and an internal voltage regulator used to compensate external variations in temperature and voltage.
Page 547: Register Descriptions
RM0400 IRCOSC digital interface 26.3.1 Register descriptions 26.3.1.1 IRCOSC Control register (IRCOSC_CTL) The IRCOSC_CTL contains user programmable parameters. Offset 00h Access: Read/Write — USER_TRIM Reset — — — — — — — Reset IRCOSC_CTL is writable only in supervisor mode. This field may sometimes have the value of 1, and can be cleared by writing a 1 to this bit.
Page 548: Table 279. Ircosc_Nt Field Descriptions
IRCOSC digital interface RM0400 Table 278. IRCOSC_CTL[USER_TRIM] frequency trimming calculation(Continued) USER_TRIM[4:0] value Frequency δf 00010 – (2 × TRIM δf 00011 – (3 × TRIM ..δf Note: See the Data Sheet for value and min/max frequency variations. TRIM 26.3.1.2 IRCOSC Native Trimming register (IRCOSC_NT) The NT register contains trim values loaded from TEST flash memory for the IRCOSC.
Page 549: Table 280. Ircosc_Tt Field Descriptions
RM0400 IRCOSC digital interface Table 279. IRCOSC_NT field descriptions(Continued) Field Description Enables temperature sensor—trimming value for safety check 0 Temperature sensor is not enabled TSENS_EN 1 Temperature sensor is enabled 22:23 Reserved 24:31 IRCOSC trimming value for safety check RCTRIM 26.3.1.3 IRCOSC Temperature Trimming register (IRCOSC_TT) The TT registers contains system trimming values for the IRCOSC that are loaded from...
Page 550: Ram Controller (Pram)
RAM controller (PRAM) RM0400 RAM controller (PRAM) 27.1 Introduction This section provides an overview of the Platform RAM Controller. The RAM controller acts as an interface between the system bus (AHB-Lite 2.v6) and the integrated system RAM. It converts the protocols between the system bus and the dedicated RAM array interface. The RAM controller supports two 32-bit AHB interfaces and a 32-bit RAM array interface.
Page 551: Memory Map And Register Definition
RM0400 RAM controller (PRAM) Figure 234. RAM controller block diagram Slave data RAMC RAM interface data bus ECC bus Master RAM interface data bus ECC bus SRAM Array(s) 27.2 Memory map and register definition The RAM controller module provides an IPS programming model mapped to a standard 16 KB on-platform peripheral slot.
Page 552: Sram Ecc Mechanism
RAM controller (PRAM) RM0400 Offset 0x00 (PRCR1) Access: Read/write 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved...
Page 553: Functional Description
RM0400 RAM controller (PRAM) Figure 236. RAM word composition RAM word 7-bit ECC 32-bit Data RAM interface ECC controller RAM module The SRAM ECC detects the following conditions and produces the following results: • Detects and corrects all 1-bit errors •...
Page 554: Initialization/Application Information
RAM controller (PRAM) RM0400 Note: The number of cycles taken for a RAM access can vary ±1 clock cycle depending on the RAM speed relative to the RAM controller clock frequency. If system RAM is running at the same frequency as the RAM controller, a random initial access takes 2 clock cycles. If system RAM is running at a slower frequency, a random initial access may take 3 clock cycles.
Page 555: Flash Memory Controller (Pflash Controller)
RM0400 Flash memory controller (PFLASH Controller) Flash memory controller (PFLASH Controller) 28.1 Introduction The flash memory controller has two functions: • It acts as an interface between the system bus (AHB-Lite 2.v6) and the flash array. • It serves as the interface to the on-chip overlay RAM and off-chip buddy device. The flash memory controller supports one 32-bit AHB buses and a 128-bit read data interface to the flash memory array.
Page 556 Flash memory controller (PFLASH Controller) RM0400 Figure 237. Platform-centric block diagram with PFLASH_MP55 flash memory controller Production Device Computational Shell e200zX Core0 PFlash Flash AMBA-AHB AXBS Cal. RAM Memory System 556/2058 DocID027809 Rev 4...
Page 557: Figure 238. Pflash_Mp55 Block Diagram
RM0400 Flash memory controller (PFLASH Controller) Figure 238. PFLASH_MP55 block diagram Way1 Way0 Mini Cache Buffer fl_rdata p0_hrdata On-Chip Overlay RAM hrdata PRAM backdoor hrdata CONTROL LOGIC fl_{rd/wr}_en Port0 haddr, fl_addr attributes buffer hit logic fl_wdata access protection hwdata logic addr generation overlay remap PRAM backdoor...
Page 558: Flash Memory Controller Memory Map
Flash memory controller (PFLASH Controller) RM0400 28.4 Flash memory controller memory map 28.4.1 Overview The flash memory controller module provides an IPS programming model mapped to a standard 16 KB on-platform peripheral slot. The programming model is partitioned into two groups: flash access configuration and overlay remapping configuration.
Page 559: Figure 239. Pfcr1 Register
RM0400 Flash memory controller (PFLASH Controller) Table 283. Flash memory controller memory map(Continued) Address Register Access Reset value Location offset 0x200 Platform Flash Calibration Region Descriptor 16 (PFCRD16) 0x0000_0000 on page 576 0x210 Platform Flash Calibration Region Descriptor 17 (PFCRD17) 0x0000_0000 on page 576 0x220...
Page 560: Table 284. Pfcr1 Field Descriptions
Flash memory controller (PFLASH Controller) RM0400 Table 284. PFCR1 field descriptions Field Description Port0 Master 15 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 15. This bit is cleared by hardware reset. P0_M15PFE 0 No prefetching may be triggered by this master 1 Prefetching may be triggered by this master Port0 Master 14 Prefetch enable.
Page 561 RM0400 Flash memory controller (PFLASH Controller) Table 284. PFCR1 field descriptions(Continued) Field Description Port0 Master 6 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 6. This bit is cleared by hardware reset. P0_M6PFE 0 No prefetching may be triggered by this master 1 Prefetching may be triggered by this master Port0 Master 5 Prefetch enable.
Page 562 Flash memory controller (PFLASH Controller) RM0400 Table 284. PFCR1 field descriptions(Continued) Field Description Read Wait State Control. This field controls the number of wait-states to be added to the best-case flash array access time for reads. The best-case flash array access time for reads is one cycle.
Page 563: Figure 241. Pfcr3 Register
RM0400 Flash memory controller (PFLASH Controller) Table 284. PFCR1 field descriptions(Continued) Field Description Port0 PFlash Prefetch Limit. This field controls the prefetch algorithm used by the prefetch controller. This field defines a limit on the maximum number of sequential prefetches which will be attempted between buffer misses.
Page 564: Table 285. Pfcr3 Field Descriptions
Flash memory controller (PFLASH Controller) RM0400 Table 285. PFCR3 field descriptions Name Description Port0 Way Configuration. This field controls the configuration of the line buffers for a given set across all four ways in the controller cache. The indexed set can be organized as a “pool”...
Page 565: Table 286. Pfapr Field Descriptions
RM0400 Flash memory controller (PFLASH Controller) Access: Supervisor Offset 0x00C Read/Write M0AP M1AP M2AP M3AP M4AP M5AP M6AP M7AP Reset M8AP M9AP M10AP M11AP M12AP M13AP M14AP M15AP Reset Figure 242. PFAPR register Table 286. PFAPR field descriptions Name Description Master 0 Access Protection.
Page 566 Flash memory controller (PFLASH Controller) RM0400 Table 286. PFAPR field descriptions(Continued) Name Description Master 4 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.
Page 567 RM0400 Flash memory controller (PFLASH Controller) Table 286. PFAPR field descriptions(Continued) Name Description Master 10 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.
Page 568: Table 287. Pfcrcr Field Descriptions
Flash memory controller (PFLASH Controller) RM0400 28.4.1.4 PFlash Calibration Remap Control Register (PFCRCR) The PFCRCR is used to globally enable/disable the calibration remap function. Access: Supervisor Offset 0x010 Read/Write Reset Reset Figure 243. PFCRCR register Table 287. PFCRCR field descriptions Field Description Safe Calibration.
Page 569: Table 288. Pfcrde Field Descriptions
RM0400 Flash memory controller (PFLASH Controller) 28.4.1.5 PFlash Calibration Remap Descriptor Enable Register (PFCRDE) The PFlash Calibration Remap Descriptor Enable Register (PFCRDE) is used to enable or disable up to 32 calibration remap descriptors. Note there is also a global remap enable (PFCRCR[GRMEN]) that also must be asserted in conjunction with the individual CRDnEN flags to enable a given remap descriptor.
Page 570 Flash memory controller (PFLASH Controller) RM0400 Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 2 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 571 RM0400 Flash memory controller (PFLASH Controller) Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 7 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 572 Flash memory controller (PFLASH Controller) RM0400 Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 12 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 573 RM0400 Flash memory controller (PFLASH Controller) Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 17 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 574 Flash memory controller (PFLASH Controller) RM0400 Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 22 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 575 RM0400 Flash memory controller (PFLASH Controller) Table 288. PFCRDE field descriptions(Continued) Field Description Calibration Remap Descriptor 27 Enable. This bit indicates whether the corresponding remap descriptor is valid. There is also a global calibration remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
Page 576: Table 289. Pflash Calibration Region Descriptor N, Word 0 Description
Flash memory controller (PFLASH Controller) RM0400 28.4.1.6 PFlash Calibration Region Descriptor n (PFCRDn) Each 96-bit (12 byte) region descriptor specifies an overlay region where a flash access can be remapped during calibration and debug. The calibration remap descriptors are organized sequentially as 128-bit (16 byte) structures in the Platform Flash Controller’s programming model.
Page 577: Table 290. Pflash Overlay Region Descriptor N, Word 1 Description
RM0400 Flash memory controller (PFLASH Controller) Access: Supervisor Offset 0x100 + (16*n) + 0x04 Read/Write PSTARTADDR Reset PSTARTADDR Reset Figure 246. PFlash Calibration Region Descriptor n, Word1 (PFCRDn.Word1) Table 290. PFlash Overlay Region Descriptor n, Word 1 description Name Description Calibration Remap Descriptor n Physical Start Address - This field defines the most significant bits of the 0-modulo-size physical start byte address of the calibration remap 0–27...
Page 578: Table 291. Pflash Overlay Region Descriptor N, Word 2 Description
Flash memory controller (PFLASH Controller) RM0400 Table 291. PFlash Overlay Region Descriptor n, Word 2 description Name Description Calibration Remap Descriptor n Master x Enable - These bits determine whether calibration remapping is performed as defined by this descriptor based on the logical master ID of the requesting AHB master.
Page 579: Functional Description
RM0400 Flash memory controller (PFLASH Controller) 28.5 Functional description As shown in Figure 237 the flash memory controller interfaces between the AHB system bus port, Nexus trace, flash memory array, overlay RAM, system RAM, and off-chip Buddy Device. For accesses targeting the flash array, the flash memory controller generates read and write enables, array address, write size and write data as inputs to the flash array.
Page 580: Read Cycles - Buffer Miss
Flash memory controller (PFLASH Controller) RM0400 28.5.3 Read cycles - buffer miss On an incoming AHB read request, a buffer lookup and access checks are performed during the AHB address phase. In the event of a buffer miss the AHB address and attributes are registered and the flash access is initiated the cycle following the AHB address phase (the first AHB data phase cycle).
Page 581: Censorship
RM0400 Flash memory controller (PFLASH Controller) 28.5.7 Censorship The entire flash space is defined by three major regions: • Code flash (instruction and constant data) • Data flash (data for EEPROM emulation) • TEST flash Each section can be independently censored, and the flash memory controller provides independent censorship control inputs for each region on a read vs.
Page 582: Instruction/Data Prefetch Triggering
Flash memory controller (PFLASH Controller) RM0400 In order for prefetching to occur, PFCR1[P0_BFEN] must be set to ‘1’, PFCR1[P0_PFLIM] must be non-zero, and either PFCR1[P0_IPFEN] or PFCR1[P0_DPFEN] must be asserted. Refer to Section 28.4.1.1, Platform Flash Configuration Register 1 (PFCR1) for a description of these controls.
Page 583: Table 292. Calibration Data Memory Base Addresses
RM0400 Flash memory controller (PFLASH Controller) To better understand the functionality of the calibration remap, consider more detailed block diagrams, one showing the overall structure of the calibration remap function and another showing more detail on the actual remap logic. Recall the flash memory controller implements a hardware interconnection matrix connecting the four input ports and four destination memories.
Page 584 Flash memory controller (PFLASH Controller) RM0400 Table 292. Calibration data memory base addresses(Continued) Calibration memory Base address Possible access sources On-chip Overlay RAM 0x0D00_---- P0, P1, PD-NAR Buddy Device (Extended) Overlay RAM 0x0C{0,1}-_---- P0, P1 Note the trace data from the Nexus Aurora Router (PD-NAR) can only be routed to the on- chip overlay RAM;...
Page 585: Figure 250. Pflash Calibration Remap Logic Detail
RM0400 Flash memory controller (PFLASH Controller) logical base address, the translated physical base address and a region size (plus other control bits). The calibration remap evaluation is initiated when the PFLASH_MP55 flash controller is presented with a flash access request from any system bus master to a location in the mirrored flash address space.
Page 586 Flash memory controller (PFLASH Controller) RM0400 Each instantiation of the basic calibration remap function {RMD0,..., RMD(n-1)} in Figure 250 includes the three descriptor registers containing the logical start address (LADDR in the figure), the physical start address (PADDR) and the region size (SZ). The region size is decoded to create the appropriate address bit enables which are then applied to the registered logical flash address.
Page 587: Safety Considerations
RM0400 Flash memory controller (PFLASH Controller) Figure 251. PFlashFlash memory controller and associated calibration remap targets Production Device Computation Shell Core0 AXBS System PRAM CTL Flash Controller Nexus Aurora Router Buffers CalRAM FLASH 28.5.13 Safety considerations 28.5.13.1 ECC Reporting The flash controller provides ECC event flags for reporting of ECC events which occur on flash and overlay RAM accesses.
Page 588 Flash memory controller (PFLASH Controller) RM0400 controller treats the 32 available calibration region descriptors (CRD0–CRD31) as a replicated group of 16 region descriptors. More specifically: • The contents of CRD0 are expected to be redundantly defined in CRD16 • The contents of CRD1 are expected to be redundantly defined in CRD17 •...
Page 589: Figure 252. Safety-Critical Calibration Remap Datapath With Redundancy
RM0400 Flash memory controller (PFLASH Controller) Figure 252. Safety-critical calibration remap datapath with redundancy system logical address CRD0 CRD0 hit? CRD0 remap addr CRD1 CRD1 hit? CRD1 remap addr CRD15 CRD15 hit? CRD hit CRD15 match? remap addr remap addr match? CRD16 CRD16 hit?
Page 590: Array Integrity Considerations
Flash memory controller (PFLASH Controller) RM0400 In the event of a non-correctable error detection, a fixed, illegal opcode value is returned to the requesting master as determined by the requesting address, and the non-correctable error event is suppressed from being reported. 28.5.13.2 Flash address generation check Functional safety coverage of the address and data are handled by ECC performed within the flash and e2eECC performed at the master.
Page 591: Embedded Flash Memory (Mp55)
RM0400 Embedded Flash Memory (MP55) Embedded Flash Memory (MP55) 29.1 Introduction The Flash Memory module serves as electrically programmable and erasable nonvolatile memory, for instructions and data storage. The Flash Memory module is a nonvolatile, solid-state silicon memory device consisting of blocks of single transistor storage elements, an electrical means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements.
Page 592: Figure 253. Flash Memory Module Structure
Embedded Flash Memory (MP55) RM0400 Figure 253. Flash memory module structure Flash memory module Flash core Flash array: 2 RWW partitions HV generator Code Flash Data Flash 1.5 MB 32 KB Partition 0 Partition 1 — — — — — — — — — — — — Flash Program/Erase Controller...
Page 593: Features
RM0400 Embedded Flash Memory (MP55) The Flash Memory module supports fault tolerance through Error Correction Code (ECC) and error detection. The ECC implemented within the Flash Memory module corrects single bit failures and detects double bit failures. The Flash Memory module uses an embedded hardware algorithm implemented in the Flash Program/Erase Controller to program and erase the Flash partitions.
Page 594: Flash Memory Map And Description
Embedded Flash Memory (MP55) RM0400 • Read mode: the Flash Memory module accepts Read accesses to the array. • Modify mode: it is possible to read and write registers, Interlock Write the memory array, program the memory array, and erase the memory array. Program and Erase operations are initiated by performing array and register writes, and controlled by an internal state machine.
Page 595: Flash Array Memory Map
RM0400 Embedded Flash Memory (MP55) 29.2.1 Flash array memory map 29.2.1.1 Code flash Partition 0 accounts for 1.5 MB of the total Flash Memory and is divided in 6 user blocks for code storage. The first 256 KB blocks are organized as 1 × 256 KB. Remaining blocks are 256 KB.
Page 596: Table 295. Testflash Block Memory Map
Embedded Flash Memory (MP55) RM0400 Table 294. Flash Memory Partition 1 memory map(Continued) Block Absolute addresses Size Address Space LOCK — — — — A256KLOCK[7] A256KSEL[7] — — — — A256KLOCK[8] A256KSEL[8] 29.2.1.3 TestFlash block memory map The TestFlash block exists outside the normal address space and is programmed, erased and read independently of the other blocks.
Page 597: Register Memory Maps And Descriptions
RM0400 Embedded Flash Memory (MP55) The TestFlash block can be enabled by the BIU.When the Test space is enabled, all the operations are mapped to the Test block.The TestFlash supports RWW and is grouped with the Code flash in partition 0. Erase of the TestFlash block is always locked in User mode.
Page 598: Register Memory Maps
Embedded Flash Memory (MP55) RM0400 Table 296. Register abbreviations Case Abbreviation Description Read/Write Software can read and write these bits. Read/Clear Software can read and clear these bits. Read/Clear Software can read and clear these bits by writing a one. Read-only Software can only read these bits.
Page 599: User Register Descriptions
RM0400 Embedded Flash Memory (MP55) Table 297. Flash User Registers memory map(Continued) Offset Description Access Reset value Location address 0x0040 Select 2 register (SEL2) 0x0000_0000 on page 616 0x0044 Reserved — — — 0x0048 Reserved — — — 0x004C Reserved —...
Page 600: Table 298. Mcr Field Descriptions
Embedded Flash Memory (MP55) RM0400 Address 0x0000 Access: User Read/Write Reset W w1c Reset Figure 254. Module Configuration Register (MCR) Table 298. MCR field descriptions Field Description Reserved (read only) 0–15 Writing to this bit has no effect and Reads always return 0. ECC event Error (Read/Clear) EER provides information on previous reads This bit must then be cleared or a reset must occur before this bit returns to a ‘0’...
Page 601 RM0400 Embedded Flash Memory (MP55) Table 298. MCR field descriptions(Continued) Field Description Single Bit Correction (Read/Clear) SBC provides information on previous reads. This bit must then be cleared or a reset must occur before this bit returns to a ‘0’ state. This bit may not be set to ‘1’...
Page 602 Embedded Flash Memory (MP55) RM0400 Table 298. MCR field descriptions(Continued) Field Description Program/Erase Good (read only) PEG is automatically updated to show the completion status of the last Flash Program or Erase sequence involving high voltage operations. PEG is evaluated on the completion status of only the interlocked doubleword during page program or quad-page programming where some doubleword addresses are not interlocked (already programmed or intended to remain virgin).
Page 603 RM0400 Embedded Flash Memory (MP55) Table 298. MCR field descriptions(Continued) Field Description Factory Erase (Read/Write). FERS is used for Erase and Program operations to enable faster operation. Factory Erase must adhere to Initial maximum (All Temperatures) conditions, with respect to voltage conditions and Write/Erase cycling.
Page 604 Embedded Flash Memory (MP55) RM0400 Table 298. MCR field descriptions(Continued) Field Description Program Suspend (Read/Write). PSUS is used to indicate that the Flash Memory module is in Program Suspend or in the process of entering a Suspend state. The Flash Memory module is in Program Suspend when PSUS=1 and DONE=1.
Page 605 RM0400 Embedded Flash Memory (MP55) Table 298. MCR field descriptions(Continued) Field Description Erase Suspend (Read/Write) ESUS is used to indicate that the Flash Memory module is in Erase Suspend or in the process of entering a Suspend state. The Flash Memory module is in Erase Suspend when ESUS=1 and DONE=1.
Page 606 Embedded Flash Memory (MP55) RM0400 Table 298. MCR field descriptions(Continued) Field Description Enable High Voltage (Read/Write) The EHV bit enables the Flash Memory module for a high voltage Program/Erase operation. EHV is cleared on reset. EHV must be set after an Interlock Write to start a Program/Erase sequence. EHV may be set under one of the following conditions: –...
Page 607: Table 299. Mcr Bits Set/Clear Priority Levels
RM0400 Embedded Flash Memory (MP55) Table 299. MCR Bits Set/Clear Priority Levels Priority level MCR bits ESUS, PSUS If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level is written. 29.3.2.2 Extended Module Configuration Register (MCRE) The Extended Module Configuration Register value is based on the size, blocks and...
Page 608 Embedded Flash Memory (MP55) RM0400 Table 300. MCRE field descriptions(Continued) Field Description Number of 256K blocks. (read only) 00000 Zero 256K blocks. 00001 One 256K block. 00010 Two 256K blocks. 00011 Three 256K blocks. 00100 Four 256K blocks. 00101 Five 256K blocks. 00110 Six 256K blocks.
Page 609 RM0400 Embedded Flash Memory (MP55) Table 300. MCRE field descriptions(Continued) Field Description Number of 64 KB blocks in mid space. (read only) 000 Zero 64 KB blocks. 001 Two 64 KB blocks. 010 Four 64 KB blocks. 16–18 011 Six 64 KB blocks. n64Km 100 Eight 64 KB blocks.
Page 610: Table 301. Lock0 Field Descriptions
Embedded Flash Memory (MP55) RM0400 29.3.2.3 Lock 0 register (LOCK0) The LOCK0 (Low/Mid Address Space Block Locking) register provides a means of protecting blocks from being modified. LOWLOCK and MIDLOCK bits corresponding to non existent blocks are read as ‘1’. To determine the effective status of the Low/Mid Address Space, combine (Or) LOCK0 with sidebands: •...
Page 611 RM0400 Embedded Flash Memory (MP55) Table 301. LOCK0 field descriptions(Continued) Field Description Low address space block lock 13-0 (Read/Write) These bits are used to lock the existing blocks of Low Address Space from Program and Erase. The block numbering for the Low Blocks starts at LOWLOCK[0] with16 KB block region (if available), then the 32 KB block region (if available), and lastly the 64 KB block region (if available).
Page 612: Table 302. Lock1 Field Descriptions
Embedded Flash Memory (MP55) RM0400 Address 0x0014 Access: User Read/Write Reset HIGHLOCK Reset Figure 257. Locking 1 register (LOCK1) Table 302. LOCK1 field descriptions Field Description Reserved (read only) 0–15 Writing to this bit has no effect and Reads always return 0. High address space block lock 15-0 (Read/Write) These bits are used to lock the blocks of High Address Space from Program and Erase.
Page 613: Table 303. Lock2 Field Descriptions
RM0400 Embedded Flash Memory (MP55) Address 0x0018 Access: User Read/Write A256KLOCK Reset A256KLOCK Reset Figure 258. Locking 2 register (LOCK2) Table 303. LOCK2 field descriptions Field Description Reserved (read only). Writing to this bit has no effect and Reads always return 0. 256K address space block lock 30-0 (Read/Write) These bits are used to lock the existing blocks of Low Address Space from Program and Erase.
Page 614: Table 304. Sel0 Field Descriptions
Embedded Flash Memory (MP55) RM0400 Address 0x0038 Access: User Read/Write LOWSEL Reset MIDSEL Reset Figure 259. Select 0 register (SEL0) Table 304. SEL0 field descriptions Field Description Reserved (read only). Writing to this bit has no effect and Reads always return 0. Low address space block select 13-0 (Read/Write) The block numbering for the Low Blocks starts at LOWSEL[0] with16 KB block region (if available), then the 32 KB block region (if available), and lastly the 64 KB block region (if...
Page 615: Table 305. Sel1 Field Descriptions
RM0400 Embedded Flash Memory (MP55) 29.3.2.7 Select 1 register (SEL1) The SEL1 (High Address Space Block Select Register 1) provides a means of selecting blocks to be operated on during Erase or Array Integrity Check – Margin Read. Starting an Erase operation, SEL1 bits are latched and become non-alterable from the first interlock cycle that follows the rising transition of MCR[ERS] (see step 4 in Section 29.4.5.5, Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR[EHV]...
Page 616: Table 306. Sel2 Field Descriptions
Embedded Flash Memory (MP55) RM0400 Starting an Erase operation, SEL2 bits are latched and become non-alterable from the first interlock cycle that follows the rising transition of MCR[ERS] (see step 4 in Section 29.4.5.5, Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR[EHV] with MCR[ERS]=1 and with MCR[ESUS]=0).
Page 617: Table 307. Adr Update Mode List
RM0400 Embedded Flash Memory (MP55) Table 307. ADR update mode list Mode Update on error Note Read ECC Double Error, ECC Single Error (if UT0.SBCE=1) — Modify FPEC error — ECC Double Error, RWW error, FPEC error, ECC Single — Error (if UT0.SBCE=1) with Break Point enabled (UT0.AIBPE=1), ADR requires...
Page 618: Table 310. Flash Memory Partition 0 Addresses Mapping
Embedded Flash Memory (MP55) RM0400 Table 309. ADR field descriptions(Continued) Field Description Address 23-3 (read only) The Address Register provides the first failing address in the event of ECC error (MCR[EER] set) or the first failing address in the event of RWW error (MCR[RWE] set), or the address of a failure that may have occurred in a FPEC operation (MCR[PEG] cleared).
Page 619: Table 311. Flash Memory Partition 1 Addresses Mapping
RM0400 Embedded Flash Memory (MP55) Table 311. Flash Memory Partition 1 addresses mapping Block Flash format addresses Absolute addresses B1F0 0x0018_0000 to 0x0018_3FFF 0x0080_0000 to 0x0080_3FFF B1F1 0x0018_4000 to 0x0018_7FFF 0x0080_4000 to 0x0080_7FFF — — — — — — — —...
Page 620 Embedded Flash Memory (MP55) RM0400 Table 312. UT0 field descriptions(Continued) Field Description Reserved (Read/Write). 2-21 Writes have no effect. For compatibility purposes, any writes should be ‘0’. Next Array Integrity Break Point (Read/Clear) If AIBPE is set, NAIBP is set once a single bit correction (if enabled) or double bit detection is noted during the Array Integrity test.
Page 621 RM0400 Embedded Flash Memory (MP55) Table 312. UT0 field descriptions(Continued) Field Description Array Integrity Sequence (Read/Write) AIS determines the address sequence to be used during Array Integrity checks. The default AIS=0 checks the read propagation paths along proprietary sequences followed by user code.
Page 622: Table 313. Um0 Field Descriptions
Embedded Flash Memory (MP55) RM0400 29.3.2.11.1 User Multiple Input Signature 0 register (UM0) UM0 represents bits 31–0 of the whole 144-bit word (2 doublewords including ECC). Address: 0x0058 Access: User Read/Write MISR Reset MISR Reset Figure 264. User Multiple Input Signature 0 register (UM0) Table 313.
Page 623: Table 315. Um2 Field Descriptions
RM0400 Embedded Flash Memory (MP55) 29.3.2.11.3 User Multiple Input Signature 2 register (UM2) UM2 represents bits 95–64 of the whole 144-bit word (2 doublewords including ECC). Address: 0x0060 Access: User Read/Write MISR Reset MISR Reset Figure 266. User Multiple Input Signature 2 register (UM2) Table 315.
Page 624: Table 317. Um8 Field Descriptions
Embedded Flash Memory (MP55) RM0400 29.3.2.11.5 User Multiple Input Signature 8 register (UM8) UM8 represents the ECC parity bits of the whole 144 bits word (8 parity bits for each of the 2 doublewords). Address: 0x0078 Access: User Read/Write MISR Reset MISR Reset...
Page 625: Table 319. Opp0 Field Descriptions
RM0400 Embedded Flash Memory (MP55) 29.3.2.12 Over-program protection registers Over-program protection prevents blocks from being over-programmed. These registers show the over-program protection status. See Section 29.4.5.3, Over-programming protection (OPP) enable. 29.3.2.12.1 Over-program protection 0 register (OPP0) The Low/Mid Address Space is covered by the Over Program Protection 0 (OPP0) register. Address: 0x0080 Access: User Read LOWOPP...
Page 626: Figure 271. Over-Program Protection 1 Register (Opp1)
Embedded Flash Memory (MP55) RM0400 Table 319. OPP0 field descriptions(Continued) Field Description Low address space Over Program Protection 13–0 (Read) The block numbering for the Low Blocks starts at LOWOPP[0] with 16 KB block region (if available), then the 32 KB block region (if available), and lastly the 64 KB block region (if available).
Page 627: Table 320. Opp1 Field Descriptions
RM0400 Embedded Flash Memory (MP55) Table 320. OPP1 field descriptions Field Description Reserved (read only) 0–15 Writing tothis bit has no effect and a read always returns 0. High address space Over Program Protection 15–0 (Read) The block numbering for the High Blocks starts at HIGHOPP[0] with 16 KB block region (if available), then the 32 KB block region (if available), and lastly the 64 KB block region (if available).
Page 628: Table 321. Opp2 Field Descriptions
Embedded Flash Memory (MP55) RM0400 Table 321. OPP2 field descriptions Field Description Reserved (read only) Writing to this bit has no effect and a read always returns 0. 256K High address space Over Program Protection 1–31 (Read) The block numbering for the 256 KB Blocks starts at A256KOPP[0] and continues until all blocks are accounted for.
Page 629: Functional Description
RM0400 Embedded Flash Memory (MP55) Table 322. TMD field descriptions Field Description The Test Mode Disable Check register is used as a location to provide a password challenge to unlock blocks selected to be sealed as part of the Test Mode Disable seal mechanism. Please Section 29.4.6.2, Test mode disable for more information.
Page 630: Low-Power Mode (Sleep Mode)
Embedded Flash Memory (MP55) RM0400 When enabled the Flash Memory module returns to its pre-disable state in all cases unless in the process of executing an Erase or a Program High Voltage operation at the time of disable. If the Flash Memory module is disabled during an Erase operation, the operation is suspended and MCR[ESUS] bits are set to ‘1’.
Page 631: Read Mode
RM0400 Embedded Flash Memory (MP55) Note: Do not enter Power-down mode when the Low-power mode is active. 29.4.4 Read mode Read mode is the active mode of operation of the Flash Memory module in which the Flash array can be read or ‘written’ (the so-called Interlock Write), or the Flash registers can be read or written.
Page 632: Table 323. Bits Manipulation: Doublewords With The Same Ecc Value
Embedded Flash Memory (MP55) RM0400 29.4.4.1 Error correction code The Flash Memory module implements a strategy for improving the reliability of the data stored in Flash via the use of Error Correction Code. The word size is fixed to 64 bits. For each doubleword of 64 bits, 8 ECC bits are associated and programmed in such a way as to guarantee Single Error Correction and Double Error Detection (SEC-DED).
Page 633: Modify Mode
RM0400 Embedded Flash Memory (MP55) Note: When some Flash blocks are used for EEPROM emulation, reserve at least 3 blocks for this purpose. 29.4.5 Modify mode All the Modify operations of the Flash Memory module are managed through the Flash User Registers interface.
Page 634 Embedded Flash Memory (MP55) RM0400 In the following sections, all the possible Modify operations are described with accompanying examples of the sequences needed to activate them. 29.4.5.1 Program A Flash Program sequence operates on any doubleword within the Flash core. Up to two words within the doubleword may be altered in a single doubleword program operation.
Page 635 RM0400 Embedded Flash Memory (MP55) The Flash Memory modules ignore address bits (23:7) for program data writes. The eventual unwritten data word defaults to 0xFFFFFFFF. Write a logic ‘1’ to MCR[EHV] to start the internal program sequence or terminate via step 9.
Page 636 Embedded Flash Memory (MP55) RM0400 } while ( !(tmp & 0x0000_0400) ); status= MCR & 0x0000_0200;/* Check PEG flag */ MCR= 0x0000_0010;/* Reset EHV in MCR: Operation End */ MCR= 0x0000_0000;/* Reset PGM: Deselect Operation */ 29.4.5.2 Program Suspend/Resume The program sequence may be suspended to allow Read access to the flash array. It is not possible to program or to erase during a Program Suspend.
Page 637 RM0400 Embedded Flash Memory (MP55) overwrite. Using these protection mechanisms in conjunction with the Test mode disable feature gives even greater overwrite protection. Attempts to over-program result in MCR[PEG] being cleared. OPP can be enabled for 16 KB, 32 KB, 64 KB and 256 KB blocks. The 256 KB blocks have selects available for the first four 256 KB blocks, and then a single select for the remainder of the 256 KB blocks.
Page 638 Embedded Flash Memory (MP55) RM0400 After setting MCR[ERS], one Write (referred to as an Interlock Write) must be performed before MCR[EHV] can be set to ‘1’. The user may terminate the Erase sequence by clearing ERS before setting EHV. An Erase operation may be aborted by clearing MCR[EHV] assuming MCR[DONE] is low, MCR[EHV] is high and MCR[ESUS] is low.
Page 639 RM0400 Embedded Flash Memory (MP55) } while ( !(tmp & 0x0000_0400) ); Note that there is no need to clear MCR[EHV] and MCR[ERS] in order to perform reads during Erase-Suspend. The Erase sequence is resumed by writing a logic ‘0’ to MCR[ESUS]. MCR[EHV] must be set to ‘1’...
Page 640 Embedded Flash Memory (MP55) RM0400 The internal MISR calculator is a 64 + 8 + 1-bit register The 128-bit data, the respective ECC parity data, and the double ECC (ERR) errors of the four doublewords are therefore captured by the MISR through 2 different Read accesses at the same location.
Page 641 RM0400 Embedded Flash Memory (MP55) Use sequential addressing for normal integrity checks of the Flash memory. If a more detailed check of the Read path is required (in diagnostic mode), leave UT0[AIS] at ‘0’ and use the proprietary address sequence that checks the Read path more completely, however this sequence takes more time.
Page 642 Embedded Flash Memory (MP55) RM0400 As with Array Integrity Check, the internal MISR calculator is a 64 + 8 + 1-bit register. The 128-bit data, the corresponding ECC parity data and the double ECC (ERR) errors of the four doublewords are therefore captured by the MISR through 2 different Read accesses at the same location.
Page 643: Protection Strategy
RM0400 Embedded Flash Memory (MP55) While UT0[AID] is low and UT0[AIE] is high, the user may abort Margin Read by clearing AIE. UT0[AID] must be checked to know when the aborting command has completed. Margin Read can be suspended by setting UT0[AISUS] while Margin Read is running (UT0[AID]=0).
Page 644: Table 325. Test Mode Disable Block Select
Embedded Flash Memory (MP55) RM0400 overall protection is obtained in conjunction with sidebands: UTEST and BAF have dedicated program protection sidebands (SoC specific). 29.4.6.2 Test mode disable In the TestFlash area a mechanism is also available to disable entry into Test mode. Extreme care must be taken when using this feature, as blocks that are selected for protection in this way cannot be analyzed for possible failures by manufacture failure analysts.
Page 645: Decorated Storage Memory Controller (Dsmc)
RM0400 Decorated Storage Memory Controller (DSMC) Decorated Storage Memory Controller (DSMC) 30.1 Introduction This section details hardware support for atomic read-modify-write memory operations. In the Power Architecture, these capabilities are called “decorated storage”. It is supported by capabilities in the processor cores plus instantiations of a Decorated Storage Memory Controller (DSMC).
Page 646: Dsmc Block Diagram
Decorated Storage Memory Controller (DSMC) RM0400 The basic decorated load or store memory reference supplements the access address and attribute information with a 32-bit “decoration”. The DSMC decoration defines the special memory operation to be performed and optionally includes bit specifiers and/or operand data for the command.
Page 647: Figure 275. Dsmc Block Diagram
RM0400 Decorated Storage Memory Controller (DSMC) Figure 275. DSMC Block Diagram s_hrdata m_haddr m_hwchkbit s_hrchkbit m_hwdata ecc_hmatrix32 ecc_hmatrix64 ecc_hmatrix64 m_multi_ecc_err s_multi_ecc_err ecc_hmatrix64_i ecc_detect64 ecc_hmatrix64_i ecc_detect64 m_single_ecc_err s_single_ecc_err hwdata[63:0] { hrchkbit[7:0], hrdata[63:0] } m_hdec*, m_hsiz, m_haddr hrdata[63:0] DSMC Operation m_hwdata[63:0] zero_result_mask[63:0] ecc_hmatrix64 s_hwdata[63:0] hrchkbit_reg[7:0]...
Page 648: Decorated Stores: St[B,H,W]D{Cb}X Rs,Rb,Ra
Decorated Storage Memory Controller (DSMC) RM0400 30.3 Decorated Stores: st[b,h,w]d{cb}x rS,rB,rA The next sections present descriptions of the specific operations, based on the 4-bit command field defined in decoration[0:3]. These descriptions include the bit pattern definitions for the 32-bit decoration value and include pseudo-code detailing the sequence of operations.
Page 649 RM0400 Decorated Storage Memory Controller (DSMC) tmp = mem[accessAddress, size] // memory read if bfw == 0 then bfw = container if ((srtbit + bfw) <= container)// generate bit mask mask = ((1 << bfw) - 1) << (container - (srtbit + bfw)) else mask = ((1 <<...
Page 650: Figure 277. Decoration Format: Cast
Decorated Storage Memory Controller (DSMC) RM0400 30.3.1.1 Compare-and-Store (CAST) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cast.b 1 0 0 1 - cast.h 1 0 0 1 - CD16 cast.w 1 0 0 1...
Page 651: Figure 279. Decoration Format: Or
RM0400 Decorated Storage Memory Controller (DSMC) 30.3.1.1.2 Logical OR (OR) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 0 0 {b,h,w Figure 279. Decoration Format: OR This command performs an atomic read-modify-write of the referenced memory location.
Page 652: Figure 281. Decoration Format: Sld
Decorated Storage Memory Controller (DSMC) RM0400 30.3.1.2.1 Simple Load (SLD) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sld. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - {b,h,w} Figure 281.
Page 653: Dsmc Timing Diagram
RM0400 Decorated Storage Memory Controller (DSMC) 30.3.1.2.3 Load-and-Set-1(Bit) (LAS1) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 las1.b 0 1 1 0 0 0 0 las1.h 0 1 1 0 0 0 las1.w 0 1 1 0 0 Figure 283.
Page 654: Dsmc Instantiations
Decorated Storage Memory Controller (DSMC) RM0400 Figure 284. DSMC Timing Diagram 30.5 DSMC Instantiations The decorated storage memory controller which performs these operations is instantiated multiple times within the core platform and physically resides between the slave ports of the crossbar and the targeted memory controllers.
Page 655: Flash Memory Programming And Configuration
RM0400 Flash Memory Programming and Configuration Flash Memory Programming and Configuration This chapter provides basic guidance on activities related to configuring and programming the embedded flash memory in the SPC572Lx microcontroller. Multiple layers of protection are available to prevent unintended updates to flash contents and unauthorized reads and writes to flash contents.
Page 656: Selection Of Flash Memory Blocks For Erase
Flash Memory Programming and Configuration RM0400 blocks. The read protection applied to a group applies to each block within the group. In contrast, secure write protection is defined at the individual block level. Secure password protection can also be implemented for the debug port. Another protection feature is the ability to configure any flash block as one-time programmable (OTP).
Page 657: Table 326. Sample Low And Mid Address Space Flash Block Bit Mapping
RM0400 Flash Memory Programming and Configuration Offset 0x0038 Access: User read/write LOWSEL[13:0] Reset MIDSEL[15:0] Reset Figure 286. SEL0 flash control register Table 326 shows an example of a mapping of SEL0 register’s LOWSEL and MIDSEL field bits to individual flash blocks .
Page 658: Non-Secure Write Protection
Flash Memory Programming and Configuration RM0400 Table 326. Sample low and mid address space flash block bit mapping(Continued) LOCKn Read LOCKn LOCKn Size Lock Bloc Start Address End Address Register Field Record Description (KB) group k No. Register DATA 0x0040_0000 0x0040_3FFF LOCK0 TSLOCK...
Page 659: Secure Write Protection
RM0400 Flash Memory Programming and Configuration secure write protection for a block, write a ‘1’ to the corresponding mapped bit found in one of the LOCK0–2 flash control registers. Note: As indicated by the reset values shown in Figure 287, after reset all blocks mapped to the register are, by default locked against programming and erase.
Page 660 Flash Memory Programming and Configuration RM0400 Note that the secure write protection settings override the non-secure write protection detailed in Section 31.2: Non-secure write protection. Implementing a custom secure write protection scheme requires creating DCF records that define the level of write protection to be applied to each flash block. The DCF records use a bit mapping scheme identical to the mapping in the flash module’s SELn and LOCKn registers.
Page 661: Implementing Secure Write Protection
RM0400 Flash Memory Programming and Configuration Figure 288. Secure write protection Flash memory region read-protection bits Flash memory block write-protection bits and debug locking bits Password 0 PASS_LOCK0PG0 PASS_LOCK1PG0 PASS_LOCK2PG0 PASS_LOCK3PG0 Password 1 PASS_LOCK0PG1 PASS_LOCK1PG1 PASS_LOCK2PG1 PASS_LOCK3PG1 Password 2 PASS_LOCK0PG2 PASS_LOCK1PG2 PASS_LOCK2PG2 PASS_LOCK3PG2...
Page 662: Figure 289. Dcf Record Structure
Flash Memory Programming and Configuration RM0400 OEM production activities. The selection becomes a permanent part of the device configuration. Configuration of blocks for secure write protection is done by writing DCF records, which is why the selection becomes a permanent part of the device. Caution: Careful planning is required before writing DCF records.
Page 663: Figure 290. Sample Dcf Record For Secure Write Protection
RM0400 Flash Memory Programming and Configuration The records defined in step <Cross Refs>2, determine the reset values of the PASS_LOCK0_PGn–PASS_LOCK3_PGn registers and therefore the write protection settings that take effect each time the microcontroller is reset. Assume four passwords have been previously implemented and the following blocks are to be locked in the password 0 group: LOCKn LOCKn...
Page 664: Overriding Secure Write Protection
Flash Memory Programming and Configuration RM0400 secured by passwords 1, 2, and 3. In contrast the blocks not secured by password 0 in this example are secured by passwords 1, 2, and 3. See the PASS section of DCF client list table (Table 71: DCF client list Chapter 8: Device Configuration Format (DCF)
Page 665: Figure 291. Lock0_Pgn Register
RM0400 Flash Memory Programming and Configuration 0x0100 LOCK0_PG0 0x0110 LOCK0_PG1 Offset Access: Read/Write 0x0120 LOCK0_PG2 0x0130 LOCK0_PG3 LOWLOCK Reset MIDLOCK Reset Figure 291. LOCK0_PGn register 1. If no DCF records have been written to change the lock state, the bit will reset to ‘1’ Note: The values in the PASS_LOCKxPGn registers override the settings in the flash module’s LOCK0–3 registers.
Page 666: Secure Read Protection
Flash Memory Programming and Configuration RM0400 LOCKn LOCKn Read Size LOCKn Bloc Start Address End Address Register Field Record Lock Description (KB) Register k No. DATA group 0x00FC_C000 0x00FC_FFFF LOCK0 LOWLOCK[4] Code Flash 0x0060_C000 0x0060_FFFF LOCK0 LOWLOCK[5] Secure Code 31.4 Secure read protection Read Protection is ability of the flash controller to block read accesses to the flash memory from all bus masters.
Page 667: Implementing Secure Read Protection
RM0400 Flash Memory Programming and Configuration Another difference is that only the PASS_LOCK3_PGn register for each password group is used: • PASS_LOCK3_PG0 • PASS_LOCK3_PG1 • PASS_LOCK3_PG2 • PASS_LOCK3_PG3 Note: The mappings of PASS_LOCK3_PGn register bits to flash blocks vary with different microcontrollers.
Page 668: Table 327. Sample Low And Mid Address Space Flash Block Bit Mapping
Flash Memory Programming and Configuration RM0400 2. If no DCF records have been written to change the lock state, the bit will reset to ‘1’. Example 16. Implementing secure read protection Assume four passwords have been previously implemented. Following is an example of a mapping of flash blocks to Read Locking groups. Table 327.
Page 669: Overriding Secure Read Protection
RM0400 Flash Memory Programming and Configuration Referring to Figure 289, the values for the DCF record are: • For LOCK3_PG0 – Data[31:0] is 0x0008_0000 (bits 0–31) – CS[14:0] is 0b000_0000_0000_1000 (bits 32–46) – Address[16:2] is 0b000_0000_0100_0011 (bits 47–61) – Parity value is irrelevant because it is not used in PASS DCF records (bit 62) –...
Page 670: Debug Port Enable/Disable
Flash Memory Programming and Configuration RM0400 First write 0b00 to the PASS_CHSEL[GRP] register field to indicate registers controlled by password 0 are to be unlocked. Write the 256-bit value for password 0 to the set of eight 32-bit password challenge input registers (PASS_CINn) beginning with PASS_CIN0.
Page 671: Unconditional Test Mode Disable Seal
RM0400 Flash Memory Programming and Configuration Optionally, the customer can create a password to enable manufacturer entry into test mode. 31.7.1 Unconditional test mode disable seal Warning: This process is not reversible. After completing these steps the SPC572Lx microcontroller is permanently prevented from entering test mode for factory analysis.
Page 672: Selecting Flash Memory Blocks For Test Mode Disable Seal
Flash Memory Programming and Configuration RM0400 Select individual flash blocks to be protected by programming the appropriate values into the Test Mode Disable Block Select Group A and Test Mode Disable Block Select Group B areas shown in the UTEST flash memory map. Program a valid passcode into the Test Mode Override Passcode area shown in the UTEST flash memory map.
Page 673: Planning Secure Write Protection
RM0400 Flash Memory Programming and Configuration Warning: The password fields are in OTP UTEST flash, so they can only be written once. 31.8.2 Planning secure write protection Up to four levels of password-secured write protection can be assigned to any block. Note that by default, all blocks of user flash are write protected, so this could be more accurately viewed as planning which blocks of user flash will not have four levels of password-secured write protection.
Page 674: Error Reporting Module (Erm)
Error Reporting Module (ERM) RM0400 Error Reporting Module (ERM) 32.1 Introduction 32.1.1 Overview The Error Reporting Module (ERM) provides information and optional interrupt notification on memory errors events associated with ECC (Error Correction Code). The ERM collects ECC events on memory accesses for platform local memory arrays, such as flash, system RAM or peripheral RAMs.
Page 675: Register Descriptions
RM0400 Error Reporting Module (ERM) Table 328. ERM memory map(Continued) Address Register Access Reset value Location offset 0x124 ERM Memory 2 Syndrome Register (ERM_SYN2) 0x0000_0000 on page 681 0x130 ERM Memory 3 Error Address Register (ERM_EAR3) 0x0000_0000 on page 681 0x134 ERM Memory 3 Syndrome Register (ERM_SYN3) 0x0000_0000...
Page 676: Table 329. Erm_Cr Field Descriptions
Error Reporting Module (ERM) RM0400 Table 329. ERM_CR field descriptions Field Description Enable Memory 0 Single Correction Interrupt Notification This field is initialized by hardware reset. 0 Interrupt notification of Memory 0 single-bit correction events is disabled. ESCIE0 1 Interrupt notification of Memory 0 single-bit correction events is enabled. Refer to the device configuration chapter for details on Memory 0 mapping.
Page 677 RM0400 Error Reporting Module (ERM) Table 329. ERM_CR field descriptions(Continued) Field Description Enable Memory 4 Non-Correctable Interrupt Notification This field is initialized by hardware reset. 0 Interrupt notification of Memory 4 non-correctable error events is disabled. ENCIE4 1 Interrupt notification of Memory 4 non-correctable error events is enabled. Refer to the device configuration chapter for details on Memory 4 mapping.
Page 678: Table 330. Erm_Sr Field Descriptions
Error Reporting Module (ERM) RM0400 Access: Supervisor Offset 0x010 Read/Write Reset Reset Figure 294. ERM Status Register (ERM_SR) Table 330. ERM_SR field descriptions Field Description Memory 0 Single-Bit Correction Event This field is initialized by hardware reset. Write ’1’ to clear this field. Write ‘1’...
Page 679 RM0400 Error Reporting Module (ERM) Table 330. ERM_SR field descriptions(Continued) Field Description Memory 2 Single-Bit Correction Event This field is initialized by hardware reset. Write ’1’ to clear this field. Write ‘1’ to clear this field also deasserts the corresponding interrupt notification if SBC2 ERM_CR[ESCIE2] is enabled.
Page 680 Error Reporting Module (ERM) RM0400 Table 330. ERM_SR field descriptions(Continued) Field Description Memory 5 Single-Bit Correction Event This field is initialized by hardware reset. Write ’1’ to clear this field. Write ‘1’ to clear this field also deasserts the corresponding interrupt notification if SBC5 ERM_CR[ESCIE5] is enabled.
Page 681: Table 331. Erm_Earn Field Description
RM0400 Error Reporting Module (ERM) 32.2.2.3 ERM Memory n Error Address Register (ERM_EARn) The ERM_EARn is a 32-bit register for capturing the address of the last ECC event in Memory n, where n denotes the memory channel. Any attempted write to ERM_EARn is ignored.
Page 682: Functional Description
Error Reporting Module (ERM) RM0400 Table 332. ERM_SYNn field descritption Field Description Memory n Syndrome - This field contains the ECC syndrome associated with the last recorded ECC event on Memory n. SYNDROME Note: Refer to the device configuration chapter for details on Memory n mapping. 32.3 Functional description 32.3.1...
Page 683: Error Injection Module (Eim)
RM0400 Error Injection Module (EIM) Error Injection Module (EIM) 33.1 Introduction 33.1.1 Overview The Error Injection Module (EIM) provides support for inducing single-bit and multi-bit inversions on read data when accessing peripheral RAMs. Injecting errors on memory accesses can be used to exercise the SEC/DED ECC function of the related system. Figure 297.
Page 684: Features
Error Injection Module (EIM) RM0400 33.1.2 Features The EIM includes these features: • supports up to six error injection channels • protection against accidental enable and reconfiguration error injection function via two-stage enable mechanism 33.2 Memory map and register definition The EIM module provides an IPS programming model mapped to a standard 16 KB on- platform peripheral slot.
Page 685: Register Descriptions
RM0400 Error Injection Module (EIM) Table 333. EIM memory map(Continued) Address Register Access Reset value Section/Page offset Error Injection Channel2 Descriptor, Word1 0x304 0x0000_0000 33.2.2.3.2/689 (EICHD2.Word1) Error Injection Channel2 Descriptor, Word2 0x308 0x0000_0000 33.2.2.3.3/690 (EICHD2.Word2) 0x30C–0x3FF Reserved Error Injection Channel3 Descriptor, Word0 0x400 0x0000_0000 33.2.2.3.1/688...
Page 686: Table 334. Error Injection Module Configuration Register (Eimcr) Field Description
Error Injection Module (EIM) RM0400 Access: Supervisor Offset 0x000 Read/Write Reset Reset Figure 298. Error Injection Module Configuration Register (EIMCR) Table 334. Error Injection Module Configuration Register (EIMCR) field description Field Description Global Error Injection Enable. This bit globally enables or disables the error injection function of the EIM. This field is initialized by hardware reset.
Page 687: Table 335. Error Injection Channel Enable Register (Eichen) Field Description
RM0400 Error Injection Module (EIM) Table 335. Error Injection Channel Enable register (EICHEN) field description Name Description Error Injection Channel 0 Enable. This bit enables the corresponding error injection channel. There is global error injection enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in Error Injection Descriptor0 registers (EICHD0) until the error injection channel is manually disabled via software.
Page 688 Error Injection Module (EIM) RM0400 Table 335. Error Injection Channel Enable register (EICHEN) field description(Continued) Name Description Error Injection Channel 4 Enable. This bit enables the corresponding error injection channel. There is a global error injection enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in Error Injection Descriptor4 registers (EICHD4) until the error injection channel is manually disabled via software.
Page 689: Table 336. Error Injection Channel N Descriptor, Word0 (Eichdn.word0) Field Description
RM0400 Error Injection Module (EIM) Access: Supervisor Offset 0x100 + (0x100*n) + 0x00 Read/Write CHKBIT_MASK Reset Reset Figure 300. Error Injection Channel n Descriptor, Word0 (EICHDn.Word0) Table 336. Error Injection Channel n Descriptor, Word0 (EICHDn.Word0) field description Name Description Checkbit Mask. This field defines a bit-mapped mask that specifies if the corresponding bit of the checkbit 31-24 bus from the target RAM should be inverted or left unmodified.
Page 690: Functional Description
Error Injection Module (EIM) RM0400 Table 337. Error Injection Channel n Descriptor, Word1 (EICHDn.Word1) field description Name Description Upper Data Mask. This field defines a bit-mapped mask that specifies if the corresponding bit of the upper 31-0 word on the read data bus from the target RAM should be inverted or left unmodified. UDATA_MASK 0 The corresponding bit of the upper word on the read data bus is left unmodified.
Page 691 RM0400 Error Injection Module (EIM) The EIM supports up to 4 error injection channels, where each channel is assigned to a single memory array interface. Each EIM channel intercepts the assigned memory read data and checkbit bus and potentially inverts the value tranmitted on each bus line as defined by EICHDn.WORD0-2.
Page 692: Analog-To-Digital Converter (Adc) Configuration
Analog-to-digital converter (ADC) configuration RM0400 Analog-to-digital converter (ADC) configuration 34.1 ADC overview This chapter is organized into the following sections: • Section 34.1, ADC overview – Section 34.1.1, ADC subsystem block diagram – Section 34.1.2, Analog input pin multiplexing • Section 34.2, Configuration of ADC modules –...
Page 693: Analog Input Pin Multiplexing
RM0400 Analog-to-digital converter (ADC) configuration Figure 303. SPC572Lx ADC subsystem VDD_HV_ADV VSS_HV_ADV 34.1.2 Analog input pin multiplexing There are 24 external analog input pins in the 100-pin QFP for SPC572Lx, and 18 in the 80- pin QFP. All analog input pins in either package are readable by SAR ADCB. In addition to DocID027809 Rev 4 693/2058...
Page 694: Configuration Of Adc Modules
Analog-to-digital converter (ADC) configuration RM0400 SAR ADCB, most analog input pins are routed to either the Sigma-Delta or SAR ADCs, but never both. Table 339 gives the analog input pin assignment for both SPC572Lx 100-pin and 80-pin packages. Table 339. SPC572Lx analog input pin multiplexing 80-pin QFP 100-pin QFP instance...
Page 695: Table 340. Sigma-Delta Adc External Signal Description
RM0400 Analog-to-digital converter (ADC) configuration 34.2.1.1 Sigma-Delta ADC external signal description The Sigma-Delta ADC external package pins for both the SPC572Lx 100-pin and 80-pin LQFPs are defined in Table 340. Table 340. Sigma-Delta ADC external signal description Signal name Signal type Signal voltage Description AN[n]...
Page 696: Figure 304. Sigma-Delta Adc Integration Diagram
Analog-to-digital converter (ADC) configuration RM0400 Figure 304. Sigma-Delta ADC integration diagram 32-bit R/W interrupt SD_CLK 4:1 Differential 8:1 Single-ended 100K 100K 100K 34.2.1.3 Sigma-Delta ADC analog input multiplexing The analog input multiplexing switches are contained within the Sigma-Delta ADC. A single analog switch pad cell is used for the Sigma-Delta analog input pins in order to share the pin with SAR ADCB.
Page 697: Figure 305. Sigma-Delta Adc Clock Diagram
RM0400 Analog-to-digital converter (ADC) configuration 34.2.1.4 Sigma-Delta ADC clock sources The Sigma-Delta ADC digital interface on the SPC572Lx has a register clock input, which is separate from the module clock input. The register interface is clocked by the PBRIDGEn_CLK. The module clock is sourced by the modulator clock (SD_CLK). See the Clocking chapter for more detail on the clock sources.
Page 698: Figure 306. Sigma-Delta Adc External Modulator Interface
Analog-to-digital converter (ADC) configuration RM0400 ADC. Currently, the AMC1203 external modulator is supported by the Sigma-Delta ADC. It is possible that other external second order modulators with clock rates less than 10 MHz and a compatible electrical interface (see SPC572Lx datasheet) could be supported. The external modulator interface for the Sigma-Delta ADC on SPC572Lx is shown in Figure 306.
Page 699: Table 341. Register Fields For Sd Adc Analog Input Channel Selection
RM0400 Analog-to-digital converter (ADC) configuration 34.2.1.7 Conversion result interrupt/DMA gating signal The Sigma-Delta ADC digital interface has an input signal that is used to disable interrupt and DMA requests for conversion results. The input signal is connected to outputs from the GTM timer block.
Page 700: Table 342. Sd Adc3 Analog Input An[X] Selection
Analog-to-digital converter (ADC) configuration RM0400 Table 342. SD ADC3 analog input AN[x] selection INP (positive INM (negative MCR_MODE MCR_VCOMSEL CSR_ANCHSEL terminal) terminal) AN[0] AN[1] AN[2] AN[3] VREFN AN[4] AN[5] AN[6] AN[7] AN[0] AN[1] AN[2] AN[3] VREFP/2 AN[4] AN[5] AN[6] AN[7] AN[0] AN[1] AN[2]...
Page 701: Table 343. Sar Adc External Signal Description
RM0400 Analog-to-digital converter (ADC) configuration The following sections describe configuration details: • Section 34.2.2.1, SAR ADC external signal description • Section 34.2.2.2, SAR ADC integration diagram • Section 34.2.2.3, SAR ADC analog input pin multiplexing • Section 34.2.2.4, SAR ADC clock sources •...
Page 702: Figure 307. Sar Adc Integration Diagram
Analog-to-digital converter (ADC) configuration RM0400 Figure 307. SAR ADC integration diagram MSCR Watchdog triggers MSCR MSCR Injection triggers TOM/ATOM input mux analog switch pad cells External pin MSCR trigger inputs SIUL2 Normal triggers SAR ADC0 AN16 Digital SAR ADC0 AN17 Interface AN24 Sigma-Delta...
Page 703: Figure 308. Sar Adc Clock Diagram
RM0400 Analog-to-digital converter (ADC) configuration 34.2.2.4 SAR ADC clock sources Each SAR ADC digital interface on SPC572Lx has a register clock input, which is separate from the module clock input. The register interface is clocked by the PBRIDGEn_CLK. The module clock is sourced by the ADC clock (SAR_CLK). See Section 21.2: Clock generation for more detail on the clock sources.
Page 704: Table 344. Sar Adc Alternate References
Analog-to-digital converter (ADC) configuration RM0400 Figure 309. SAR ADC input trigger diagram System Integration injected conversion start signal Digital SARB normal conversion External injected conversion Digital SAR0 Pins normal conversion channel outputs injected conversion Digital SAR4 normal conversion Trigger source selection for each SAR ADC is given in the SIUL2 chapter of this document. 34.2.2.6 SAR ADC alternate reference The SAR ADCs support connection to more than one conversion reference.
Page 705: Figure 310. Self Test Implementation
RM0400 Analog-to-digital converter (ADC) configuration 34.2.2.8 SAR ADC diagnostic 34.2.2.8.1 Self Test features Following are the Self Test features: • The ADCBIAS provides four different voltage levels defined as GND, V /3 , 2 × V and V . The tolerance of these middle two generated voltages is 4% of V considered to be from 4 V to 6 V).
Page 706: Figure 311. Analog Input Pin Pull Up/Down Pad Cell
Analog-to-digital converter (ADC) configuration RM0400 34.2.2.8.2 Internal reference The SARB ADC provides the ability to sample and convert four internal voltages through a 20 kΩ source impedance. These voltages are as follows: • DD_HV_ADR • 1/3 V DD_HV_ADR • 2/3 V DD_HV_ADR •...
Page 707: Table 345. Sar Adc Analog Input Channel Assignment
RM0400 Analog-to-digital converter (ADC) configuration Figure 312. Analog input AN35 — discharge switch to AVSS SIUL2 MSCR SIUL2 MSCR VDD_HV_ADV dual analog switch SAR ADCB AN35 SAR ADC4 pull up/down switch to ground analog input pad cell VSS_HV_ADV The ground switches for AN7/AN35 are controlled independently from the input switch to the ADC.
Page 708: Table 346. Sarb Analog Test Channel Assignment
Analog-to-digital converter (ADC) configuration RM0400 Table 346. SARB analog test channel assignment SARB input Description channel VDD_HV_PMC 97–103 Reserved VDD_LV 105–108 Reserved VSS_HV_ADV (ADC Ground Voltage) 110–119 Reserved Temperature Sensor ADC Bandgap Reference 122–123 Reserved Ω SAR BIAS 0—V through 20 k source impedance SS_HV_ADR Ω...
Page 709: Table 347. Sar Adc Register Descriptions
RM0400 Analog-to-digital converter (ADC) configuration Figure 313. SARB ADC read of internal PMC voltages SARB input switch matrix SARB analog mux n channel SoC mux SARB input switch matrix SARB Digital Interface switch decode One-hot switch code (110) PMC Digital Interface 34.2.2.10 SAR ADC register definitions Each of the following sections shows register definitions for one SAR ADC instance: •...
Page 710: Table 348. Sar Adc Test Channel Register Descriptions (Sarb Only)
Analog-to-digital converter (ADC) configuration RM0400 Table 347. SAR ADC register descriptions(Continued) Name Description User access ICDSRn Internal Channel DMA Select Registers read/write WTHRHLR0–3 Watchdog Threshold Registers 0–3 read/write CTRn Conversion Timing Registers 0–3 read/write ICNCMRn Internal Channel Normal Conversion Mask Registers read/write ICJCMRn Internal Channel Injected Conversion Mask Registers...
Page 711: Table 350. Sar Adcb Register Definitions
RM0400 Analog-to-digital converter (ADC) configuration Table 349. SAR ADC external channel register descriptions (SARB only)(Continued) Name Description User access ECWENRn External Channel Watchdog Enable Registers read/write ECAWORRn External Channel Analog Watchdog Out of Range registers read ECMICRn External Channel Mapping to Internal Channel Registers read/write ECDR128–191 External Channel Data Registers 128–191...
Page 712 Analog-to-digital converter (ADC) configuration RM0400 Table 350. SAR ADCB register definitions(Continued) Name SARADCB_ICIPR0 SARADCB_ICIPR1 SARADCB_IMR SARADCB_ICIMR0 712/2058 DocID027809 Rev 4...
Page 713 RM0400 Analog-to-digital converter (ADC) configuration Table 350. SAR ADCB register definitions(Continued) Name SARADCB_ICIMR1 SARADCB_WTISR SARADCB_WTIMR SARADCB_DMAE SARADCB_ICDSR0 SARADCB_ICDSR1 DocID027809 Rev 4 713/2058...
Page 714 Analog-to-digital converter (ADC) configuration RM0400 Table 350. SAR ADCB register definitions(Continued) Name THRH SARADCB_ WTHRHLR0– WTHRHLR3 THRL SARADCB_CTR0–3 PRECHG INPSAMP SARADCB_ICNCMR0 SARADCB_ICNCMR1 SARADCB_ICJCMR0 SARADCB_ICJCMR1 714/2058 DocID027809 Rev 4...
Page 715 RM0400 Analog-to-digital converter (ADC) configuration Table 350. SAR ADCB register definitions(Continued) Name SARADCB_PDEDR PDED SARADCB_ICDR0–3, RESULT CTSEL ICDR8, ICDR10–13, ICDR16–21, ICDR24– 29, ICDR32–33, ICDR36–39, ICDR44– CDATA 53, ICDR56–61 RESULT CTSEL SARADCB_ICDR4–7, ICDR35 CDATA THRH SARADCB_ WTHRHLR4– WTHRHLR7 THRL WSEL_CH7 WSEL_CH6 WSEL_CH5 WSEL_CH4 SARADCB_ICWSELR0...
Page 716 Analog-to-digital converter (ADC) configuration RM0400 Table 350. SAR ADCB register definitions(Continued) Name WSEL_CH29 WSEL_CH28 SARADCB_ICWSELR3 WSEL_CH27 WSEL_CH26 WSEL_CH25 WSEL_CH24 WSEL_CH39 WSEL_CH38 WSEL_CH37 WSEL_CH36 SARADCB_ICWSELR4 WSEL_CH35 WSEL_CH33 WSEL_CH32 WSEL_CH47 WSEL_CH46 WSEL_CH45 WSEL_CH44 SARADCB_ICWSELR5 WSEL_CH53 WSEL_CH52 SARADCB_ICWSELR6 WSEL_CH51 WSEL_CH50 WSEL_CH49 WSEL_CH48 WSEL_CH61 WSEL_CH60 SARADCB_ICWSELR7 WSEL_CH59...
Page 717 RM0400 Analog-to-digital converter (ADC) configuration Table 350. SAR ADCB register definitions(Continued) Name SARADCB_ICAWORR SARADCB_ICAWORR DocID027809 Rev 4 717/2058...
Page 718: Table 351. Sar Adcb Test Channel Register Definitions
Analog-to-digital converter (ADC) configuration RM0400 Table 351. SAR ADCB test channel register definitions Name SARADCB_TCIPR SARADCB_TCIMR SARADCB_TCDSR SARADCB_TCNCMR 718/2058 DocID027809 Rev 4...
Page 719 RM0400 Analog-to-digital converter (ADC) configuration Table 351. SAR ADCB test channel register definitions(Continued) Name SARADCB_TCJCMR WSEL_CH10 WSEL_CH10 SARADCB_TCWSELR WSEL_CH99 WSEL_CH98 WSEL_CH97 WSEL_CH96 WSEL_CH10 WSEL_CH10 WSEL_CH110 SARADCB_TCWSELR WSEL_CH10 WSEL_CH10 WSEL_CH119 WSEL_CH118 WSEL_CH117 WSEL_CH116 SARADCB_TCWSELR WSEL_CH115 WSEL_CH114 WSEL_CH113 WSEL_CH112 WSEL_CH12 WSEL_CH12 WSEL_CH12 WSEL_CH12 SARADCB_TCWSELR WSEL_CH12...
Page 720 Analog-to-digital converter (ADC) configuration RM0400 Table 351. SAR ADCB test channel register definitions(Continued) Name SARADCB_TCAWORR ICSEL_TCH99 ICSEL_TCH98 SARADCB_TCCAPR0 ICSEL_TCH97 ICSEL_TCH96 SARADCB_TCCAPR1 ICSEL_TCH101 ICSEL_TCH100 ICSEL_TCH106 SARADCB_TCCAPR2 ICSEL_TCH104 720/2058 DocID027809 Rev 4...
Page 721 RM0400 Analog-to-digital converter (ADC) configuration Table 351. SAR ADCB test channel register definitions(Continued) Name ICSEL_TCH110 SARADCB_TCCAPR3 ICSEL_TCH109 ICSEL_TCH108 ICSEL_TCH115 ICSEL_TCH114 SARADCB_TCCAPR4 ICSEL_TCH113 ICSEL_TCH112 ICSEL_TCH119 ICSEL_TCH118 SARADCB_TCCAPR5 ICSEL_TCH117 ICSEL_TCH116 ICSEL_TCH122 SARADCB_TCCAPR6 ICSEL_TCH121 ICSEL_TCH120 DocID027809 Rev 4 721/2058...
Page 722: Table 352. Sar Adcb External Channel Register Definitions
Analog-to-digital converter (ADC) configuration RM0400 Table 351. SAR ADCB test channel register definitions(Continued) Name ICSEL_TCH127 ICSEL_TCH126 SARADCB_TCCAPR7 ICSEL_TCH125 ICSEL_TCH124 SARADCB_ RESULT TCDR96–101 CTSEL TCDR104, TCDR106, TCDR108–TCDR110, TCDR112–114, CDATA TCDR116–118, TCDR120–127 Table 352. SAR ADCB external channel register definitions Name SARADCB_ECDSDR SARADCB_ECIPR0 722/2058 DocID027809 Rev 4...
Page 723 RM0400 Analog-to-digital converter (ADC) configuration Table 352. SAR ADCB external channel register definitions(Continued) Name SARADCB_ECIMR0 SARADCB_ECDSR0 SARADCB_ECNCMR0 SARADCB_ECJCMR0 WSEL_CH13 WSEL_CH13 WSEL_CH13 WSEL_CH13 SARADCB_ECWSELR0 WSEL_CH13 WSEL_CH13 WSEL_CH12 WSEL_CH12 DocID027809 Rev 4 723/2058...
Page 724 Analog-to-digital converter (ADC) configuration RM0400 Table 352. SAR ADCB external channel register definitions(Continued) Name SARADCB_ECWENR0 SARADCB_ECAWORR SARADCB_ECMICR0 ICSEL_ECH128_135 RESULT CTSEL SARADCB_ ECDR128– CDATA 724/2058 DocID027809 Rev 4...
Page 725: Table 353. Sar Adc0 Register Definitions
RM0400 Analog-to-digital converter (ADC) configuration 34.2.2.10.2 SAR ADC0 register definitions Table 353. SAR ADC0 register definitions Name SARADC0_MCR JTRGSEL SARADC0_MSR CHADDR ADCSTATUS SARADC0_ISR SARADC0_ICIPR0 SARADC0_IMR DocID027809 Rev 4 725/2058...
Page 726 Analog-to-digital converter (ADC) configuration RM0400 Table 353. SAR ADC0 register definitions(Continued) Name SARADC0_ICIMR0 SARADC0_WTISR SARADC0_WTIMR SARADC0_DMAE SARADC0_ICDSR0 THRH SARADC0_ WTHRHLR0– WTHRHLR3 THRL 726/2058 DocID027809 Rev 4...
Page 727 RM0400 Analog-to-digital converter (ADC) configuration Table 353. SAR ADC0 register definitions(Continued) Name SARADC0_CTR0–3 PRECHG INPSAMP SARADC0_ICNCMR0 SARADC0_ICJCMR0 SARADC0_PDEDR PDED RESULT CTSEL SARADC0_ICDR4–8, ICDR10–13 CDATA WSEL_CH7 WSEL_CH6 WSEL_CH5 WSEL_CH4 SARADC0_ICWSELR0 DocID027809 Rev 4 727/2058...
Page 728: Table 354. Sar Adc4 Register Definitions
Analog-to-digital converter (ADC) configuration RM0400 Table 353. SAR ADC0 register definitions(Continued) Name WSEL_CH13 WSEL_CH12 SARADC0_ICWSELR1 WSEL_CH11 WSEL_CH10 WSEL_CH8 SARADC0_ICWENR0 SARADC0_ICAWORR0 34.2.2.10.3 SAR ADC4 register definitions Table 354. SAR ADC4 register definitions Name SARADC4_MCR JTRGSEL SARADC4_MSR CHADDR ADCSTATUS 728/2058 DocID027809 Rev 4...
Page 729 RM0400 Analog-to-digital converter (ADC) configuration Table 354. SAR ADC4 register definitions(Continued) Name SARADC4_ISR SARADC4_ICIPR1 SARADC4_IMR SARADC4_ICIMR1 SARADC4_WTISR SARADC4_WTIMR DocID027809 Rev 4 729/2058...
Page 730 Analog-to-digital converter (ADC) configuration RM0400 Table 354. SAR ADC4 register definitions(Continued) Name SARADC4_DMAE SARADC4_ICDSR1 THRH SARADC4_ WTHRHLR0– WTHRHLR3 THRL SARADC4_CTR0–3 PRECHG INPSAMP SARADC4_ICNCMR1 SARADC4_ICJCMR1 SARADC4_PDEDR PDED 730/2058 DocID027809 Rev 4...
Page 731 RM0400 Analog-to-digital converter (ADC) configuration Table 354. SAR ADC4 register definitions(Continued) Name RESULT CTSEL SARADC4_ICDR32– ICDR35, ICDR44–47 CDATA SARADC4_ICWSELR4 WSEL_CH35 WSEL_CH33 WSEL_CH32 WSEL_CH47 WSEL_CH46 WSEL_CH45 WSEL_CH44 SARADC4_ICWSELR5 SARADC4_ICWENR1 SARADC4_ICAWORR1 DocID027809 Rev 4 731/2058...
Page 732: Sigma-Delta Analog-To-Digital Converter (Sdadc) Digital Interface
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface 35.1 Introduction The Sigma-Delta Analog-to-Digital Converter (SDADC) digital interface block controls the on-chip SDADC and holds control and status registers accessible for application. It provides accurate conversion data for a wide range of applications. 35.2 Overview Figure 314...
Page 733: Figure 314. Sdadc Block Diagram
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Figure 314. SDADC block diagram 32-bit R/W interrupt SD_CLK 4:1 Differential 8:1 Single-Ended 100K 100K 100K DocID027809 Rev 4 733/2058...
Page 734: Features
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 35.3 Features • 16-bit data resolution output • Single-ended input or differential input mode of operation • Programmable wraparound mechanism for both modes of operation – Configurable trigger sources: hardware or software – Configurable initial entry and wraparound values for the loop •...
Page 735: External Signal Description
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface from the external modulator. The external pin function control for these pins must be configured in the integration logic on a device, and is not included in the SDADC digital interface. 35.5 External signal description Table 355 shows the list of signals driven by external pins.
Page 736: Memory Map And Register Descriptions
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Table 356. Detailed signal descriptions(Continued) Signal Description Clock input provided by external modulator. Asserted—clock high level State meaning Negated—clock low level EMCLK Assertion—May occur at any time, but clock is valid only when external modulator Timing is selected by MCR[MODSEL] = 1.
Page 737: Table 358. Mcr Field Descriptions
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Offset 0x0000 Access: User Read/Write PGAN Reset TRIGSEL Reset Figure 315. Module Configuration Register (MCR) Table 358. MCR field descriptions Field Description 0–2 Reserved Programmable Decimation Rate This field selects the over-sampling ratio to be applied to support different passbands with a fixed input sampling clock.
Page 738 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Table 358. MCR field descriptions(Continued) Field Description Reserved Programmable Gain This field selects the gain to be applied to the analog input stage of the SDADC. The effective analog input becomes the input voltage level multiplied by the gain factor. 000 Gain = 1 001 Gain = 2 9–11...
Page 739 RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Table 358. MCR field descriptions(Continued) Field Description Freeze This field enables stopping the SDADC conversions at the end of the current channel conversion when the SoC enters debug mode. When the SoC enters debug mode, further conversions by the SDADC analog block will be stopped, and converted data output from the SDADC analog block are ignored.
Page 740: Table 359. Csr Field Descriptions
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Offset 0x0004 Access: User Read/Write BIASEN Reset ANCHSEL_WRAP ANCHSEL Reset Figure 316. Channel Selection Register (CSR) Table 359. CSR field descriptions Field Description 0–7 Reserved Bias enable 8–15 If BIASEN[i] = 1, analog input AN[i] (could be single-ended input or differential analog input) is BIASEN[7:0] connected to half-scale bias through a 100 KΩ...
Page 741: Table 360. Analog Input An[0:7] Selection
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Table 360. Analog input AN[0:7] selection INP (positive INM (negative MODE VCOMSEL ANCHSEL terminal) terminal) AN[0] AN[1] AN[2] AN[3] VREFN AN[4] AN[5] AN[6] AN[7] AN[0] AN[1] AN[2] AN[3] VREFP/2 AN[4] AN[5] AN[6] AN[7] AN[0] AN[1] AN[2]...
Page 742: Table 361. Rkr Field Descriptions
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Offset 0x0008 Access: User Read/Write Reset RESET_KEY Reset Figure 317. Reset Key Register (RKR) Table 361. RKR field descriptions Field Description 0–15 Reserved Reset Key This field, when written with 0x5AF0, is used to generate the reset for the SDADC block and 16–31 to reload the internal counter with the start value programmed in OSDR.
Page 743: Table 362. Sfr Field Descriptions
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Table 362. SFR field descriptions Field Description 0–12 Reserved Analog Channel Selection Counter(ANCHSEL_CNT) 13–15 This field reflects the current value of the internal Analog Channel Selection Counter. It ANCHSEL_CNT indicates the present number of the channel selected through the analog multiplexer. 16–22 Reserved Data FIFO Empty Flag...
Page 744: Table 363. Rser Field Descriptions
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 35.6.2.5 Request Select and Enable Register (RSER) The Request Select and Enable Register (RSER) serves two purposes: • Enables the flag bits in SFR to generate DMA requests or interrupt requests. • Selects the type of request to generate. Refer to the field descriptions for the type of requests that are supported.
Page 745: Figure 320. Output Settling Delay Register (Osdr)
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Table 363. RSER field descriptions(Continued) Field Description Data FIFO Overrun Interrupt Enable This bit enables the SFR[DFORF] field to generate an interrupt request. The final interrupt request also depends on the gating signal if enabled by the GDIGE field. DFORIE 0 Interrupt request is disabled when data FIFO overrun condition occurs 1 Interrupt request is enabled when data FIFO overrun condition occurs...
Page 746: Table 364. Osdr Field Descriptions
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Table 364. OSDR field descriptions Field Description 0–23 Reserved Output Settling Delay This field defines the delay to qualify the conversion data stored in CDR. Whenever the SDADC block is reset in order to start the conversion from a fresh state, an internal timer is loaded with this start value.
Page 747: Figure 322. Software Trigger Key Register (Stkr)
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Table 365. FCR field descriptions(Continued) Field Description FIFO Threshold When the number of datawords in the data FIFO is greater than the value in FTHLD field, the 20–23 FIFO full event is flagged. An interrupt or a DMA request will be generated as determined by FTHLD DFFDIRE and DFFDIRS fields of RSER.
Page 748: Functional Description
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Table 366. STKR field descriptions Field Description 0–15 Reserved Software Trigger Key This bitfield, when written with 0xFFFF, is used to generate a trigger event output which can 16–31 be used to trigger conversions of multiple SDADC blocks synchronously depending on the ST_KEY[15:0] SoC implementation.
Page 749: Differential Input Mode
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface 35.7.1 Differential input mode After system reset exit, this is the default mode of operation if SDADC is enabled by asserting MCR[EN]. This mode is entered by negating MCR[MODE]. In differential input mode, a pair of analog inputs among AN[0:7] is connected to the input terminals of the SDADC modulator block.
Page 750: Programmable Gain And Decimation Rate
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 35.7.6 Programmable gain and decimation rate All analog inputs can be configured to have a selectable input gain as defined in the PGAN field description in MCR. This means the input signal is sampled and the result is amplified by the factor determined by PGAN before providing the same to modulator.
Page 751: Hardware Triggering
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface wraparound mode, definition of ANCHSEL and ANCHSEL_WRAP is provided in Table 360: Analog input AN[0:7] selection. • Upon entering or during wraparound mode user should take care to program ANCHSEL value < ANCHSEL_WRAP value, otherwise hardware would reject the new ANCHSEL value.
Page 752: Interrupt/Dma Request Support
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 In case of a hardware trigger, the skew/jitter will be less than 100 ns. It will be more than one ADC clock cycle due to synchronization. In case of a software trigger, all SDADCs start synchronous sampling.
Page 753: Offset Calibration Support
RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface process. Dn is the average value of attenuated negative full scale given by Dn = AVERAGE(CDR[CDATA]). 11. The SDADC calibrated gain can be calculated as: Gain = (D – D ) / 2 12.
Page 754: Data Conversion Step
Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface RM0400 Enable the SDADC by asserting MCR[EN]. Configure MCR to select the required mode, polarity, common mode voltage, input gain, and decimation rate. Enable high-pass filter if required. Select the required analog channel for data conversion. It is possible to select the bias for each channel for AC coupling applications.
Page 755 RM0400 Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface Note: where:CLK_Out = CLK_In/(2*OSR) DocID027809 Rev 4 755/2058...
Page 756: Introduction
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Successive Approximation Register Analog-to- Digital Converter (SARADC) Digital Interface 36.1 Introduction The Successive Approximation Register Analog-to-Digital Converter (SARADC) digital interface block controls the on-chip SARADC analog block and holds control and status registers accessible for the application.
Page 757: Figure 324. Saradc Block Diagram
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Figure 324. SARADC block diagram SoC Input Switch Network REFH_ADC REFH_ADC DD_HV_ADC_TSENS SAR ADC Digital Interface switch control Precharge ctrl TCCAPR7[ICSEL_TCH3] Bias Generator Ω bias current TCCAPR7[ICSEL_TCH1] TCCAPR7[ICSEL_TCH2] REFL_ADC SS_HV_ADC REFL_ADC _TSENS TCCAPR7[ICSEL_TCH0] Note:...
Page 758: Feature Description
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface 36.3 Feature description 36.3.1 Main features • Selectable 10-bit or 12-bit data resolution output • Up to 96 internal channels, 32 test channels; variable number of analog channels of each type controlled by parameters •...
Page 759: Figure 325. Normal Conversion Flow
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.4.1.1 Start of normal conversion The normal conversion can be started as follows: • By software – The normal conversion chain starts when the MCR[NSTART] bit is set. The normal trigger enable MCR[NTRGEN] bit should be reset during conversions started by software.
Page 760: Injected Channel Conversion
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface after the current conversion is finished. This is called enqueuing. Enqueuing can help in removing the delay between two consecutive one shot chains and uncertainty caused by metastability between MCR[NSTART] bit written at system clock and generation of start pulse on ADC clock before every chain execution.
Page 761: Abort Conversion
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- The injected conversion can be started as follows: • By software – The injected conversion chain starts when the MCR[JSTART] bit is set. The current conversion is suspended and the injected chain is converted. At the end of the chain, the MSR[JSTART] bit is reset and the normal chain conversion is resumed.
Page 762: Analog Conversion Timings And Reference Selection
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface generating an ECH interrupt. ABORT function should not be used when only single channel is selected in a conversion chain, instead ABORTCHAIN can be used. • It is also possible to abort the current chain conversion by setting the ABORTCHAIN bit in the MCR.
Page 763: Test Channel Connection With Internal Analog Channel
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- The sampling phase duration is given by the following equation: = INPSAMP * t sample where INPSAMP must be greater than or equal to 5 (hardware requirement). In case the value of INPSAMP is found to be less than 5, it is automatically set to 5 inside SARADC. The total evaluation phase duration is given by the following equations: = 12 * t eval...
Page 764: Programmable Analog Watchdog
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface channel to any internal analog channel is determined by the ICSEL_TCHx bitfield of TCCAPR0–7 registers. For analog test channel assignment, refer to the device configuration or ADC configuration section. After the conversion is performed on a test channel the converted data is stored at two CDR locations at the end of conversion, first location is the CDR belonging to the test channel on which conversion is performed and second location is the CDR belonging to internal channel on which test channel is mapped.
Page 765: Dma Functionality
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- threshold values. Enabling is done by setting the bit corresponding to channel 30 in ICWENR0 register. If the converted value for a particular channel lies outside the range specified by threshold values, then the corresponding bit is set in ICAWORR0–2, TCAWORR, ECAWORR0–3 registers.
Page 766: Power Down Mode
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface The ISR[NECH] bit is set when a normal channel conversion chain is completed. This pending status is qualified when the corresponding mask bit IMR[MSKNECH] is also set. The ISR[JECH] bit is set when an injected channel conversion chain is completed. This pending status is qualified when the corresponding mask bit IMR[MSKNECH] is also set.
Page 767: Table 369. Saradc Digital Interface Register Map
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Note: The actual availability and number of registers and their configuration are chip-specific. For this information, see "Device Configuration" chapter. Table 369. SARADC digital interface register map Register Offset Register Location classification 36.5.1.1 on 0x000...
Page 768 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 369. SARADC digital interface register map(Continued) Register Offset Register Location classification 0x0CC–0x0FC Reserved 36.5.1.16 on 0x100–0x27C Internal Channel Data Registers 0–95 (ICDR0–ICDR95) Saf-Relv page 784 36.5.1.17 on 0x280–0x2AC Watchdog Threshold Registers 4-15 (WTHRHLR4-WTHRHLR15) Saf-Relv page 935 0x280–0x2AC...
Page 769: Register Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.5.1 Register descriptions 36.5.1.1 Main Configuration Register (MCR) Offset 0x000 Access: User Read/Write Reset JTRGSEL Reset 1. These bits may be written, but will have no effect on the device. 2. This bit is not available on this device and is thus reserved. Figure 329.
Page 770 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 370. MCR field descriptions(Continued) Field Description Normal trigger edge selection 6–7 00 Falling edge of normal trigger is selected. NEDGESEL[1:0] 01 Rising edge of normal trigger is selected. 1x Both rising and falling edges of normal trigger are selected. (x = 0,1) Injected Start conversion Setting this bit will start the configured injected analog channels to be converted by software.
Page 771: Figure 330. Main Status Register (Msr)
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Table 370. MCR field descriptions(Continued) Field Description Reserved Freeze This bit enables to stop the SARADC conversions at the end of current channel conversion when SoC enters debug mode. 0 Conversions are not stopped. 1 When SoC enters debug mode, further conversions by SARADC analog block will be stopped.
Page 772: Table 371. Msr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 371. MSR field descriptions Field Description Reserved 0–3 Write of any value has no effect; read value is always 0. This status bit is used to signal that a normal conversion is ongoing. 0 Normal conversion is not taking place.
Page 773: Table 372. Isr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.5.1.3 Interrupt Status Register (ISR) Offset 0x010 Access: User Read Only Reset Reset 1. Only available with cross-triggering unit (CTU) feature. Figure 331. Interrupt Status Register (ISR) Table 372. ISR field descriptions Field Description Reserved...
Page 774: Table 373. Icipr0–Icipr2 Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface 36.5.1.4 Internal Channel Interrupt Pending Registers 0–2 (ICIPR0–ICIPR2) The interrupt channel register to channel association is described in Table 374. Offset 0x014–0x01C Access: User Read Only EOC_CH[x] Reset EOC_CH[x] Reset Figure 332. Internal Channel Interrupt Pending Registers (ICIPR0–ICIPR2) Table 373.
Page 775: Table 375. Imr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Offset 0x020 Access: User Read/Write Reset Reset 1. Not funtionally used, but this bit can be written by software. 2. Only available with cross-triggering unit (CTU) feature. Figure 333. Interrupt Mask Register (IMR) Table 375.
Page 776: Table 376. Icimr0–Icimr2 Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Offset 0x024–0x02C Access: User Read/Write IM_CH[x] Reset IM_CH[x] Reset Figure 334. Internal Channel Interrupt Mask Registers (ICIMR0–ICIMR2) Table 376. ICIMR0–ICIMR2 field descriptions Field Description IM_CH[x]: Interrupt mask bit for channel x 0–31 0 Interrupt for CH[x] is disabled.
Page 777: Table 378. Wtisr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Offset 0x030 Access: User Read Only W w1c Reset W w1c Reset Figure 335. Watchdog Threshold Interrupt Status Register (WTISR) Table 378. WTISR field descriptions Field Description This corresponds to the interrupt generated on the converted value being higher 2x+1 than the programmed higher threshold as reported by WDG monitor ‘x’.
Page 778: Table 379. Wtimr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Offset 0x034 Access: User Read/Write Reset Reset Figure 336. Watchdog Threshold Interrupt Mask Register (WTIMR) Table 379. WTIMR field descriptions Field Description This corresponds to the mask bit for the interrupt generated on the converted value 2x+1 being higher than the programmed higher threshold.
Page 779: Table 380. Dmae Register Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Offset 0x040 Access: User Read/Write Reset Reset Figure 337. DMA Enable Register (DMAE) Table 380. DMAE register field descriptions Field Description Reserved 0–29 Write of any value has no effect; read value is always 0. DMA clear sequence enable 0 DMA request cleared by Acknowledge from DMA controller DCLR...
Page 780: Table 381. Icdsr0–Icdsr2 Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 381. ICDSR0–ICDSR2 field descriptions Field Description DMA select for channel x 0–31 0 CH[x] is disabled to transfer data in DMA mode. DS_CH[x] 1 CH[x] is enabled to transfer data in DMA mode. Table 382.
Page 781: Table 384. Ctr0–Ctrl3 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.5.1.12 Conversion Timing Registers 0–3 (CTR0–CTRL3) Offset 0x094–0x0A0 Access: User Read/Write Reset PRECHG INPSAMP Reset Figure 340. Conversion Timing Registers 0–3 (CTR0–CTRL3) Table 384. CTR0–CTRL3 field descriptions Field Description Conversion Resolution select This bit selects the conversion resolution for the conversion.
Page 782: Table 385. Icncmr0–Icncmr2 Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Offset 0x0A4–0x0AC Access: User Read/Write NCE_CH[x] Reset NCE_CH[x] Reset Figure 341. Internal Channel Normal Conversion Mask Registers (ICNCMR0–ICNCMR2) Table 385. ICNCMR0–ICNCMR2 field descriptions Field Description Normal conversion enable for channel x 0–31 0 Normal conversion is disabled for CH[x].
Page 783: Table 387. Icjcmr0–Icjcmr2 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Offset 0x0B4–0x0BC Access: User Read/Write JCE_CH[x] Reset JCE_CH[x] Reset Figure 342. Internal Channel Injected Conversion Mask Registers (ICJCMR0–ICJCMR2) Table 387. ICJCMR0–ICJCMR2 field descriptions Field Description Injected conversion enable for channel x 0–31 0 Injected conversion is disabled for CH[x].
Page 784: Table 389. Pdedr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface 36.5.1.15 Power Down Exit Delay Register (PDEDR) Offset 0x0C8 Access: User Read/Write Reset PDED Reset Figure 343. Power Down Exit Delay Register (PDEDR) Table 389. PDEDR field descriptions Field Description Reserved 0–23 Write of any value has no effect;...
Page 785: Table 390. Icdr0–Icdr95 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Table 390. ICDR0–ICDR95 field descriptions Field Description Reserved Write of any value has no effect; read value is always 0. Reference selection This bit can be used to select the reference voltage for channel conversion. 0 Selects the default reference (e.g., : 5 V) REFSEL 1 Selects the alternate reference (e.g., : 2 V)
Page 786: Figure 345. Watchdog Threshold Registers 4–15 (Wthrhlr4–Wthrhlr15)
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 390. ICDR0–ICDR95 field descriptions(Continued) Field Description Conversion result mode status This bit reflects the mode of conversion for the corresponding channel. 14–15 00 Data is a result of Normal conversion mode RESULT[1:0] 01 Data is a result of Injected conversion mode 10 Data is a result of CTU conversion mode...
Page 787: Table 391. Wthrhlr4–Wthrhlr15 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Table 391. WTHRHLR4–WTHRHLR15 field descriptions Field Description Reserved 0–3 Write of any value has no effect; read value is always 0. 4–15 High threshold value for channel x THRH Reserved 16–19 Write of any value has no effect;...
Page 788: Table 393. Internal Channel Watchdog Enable Registers To Channel Association
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 393. Internal Channel Watchdog Enable Registers to Channel Association Register Register bits 31:0 ICWSELRx (x = 0 to 11) WSEL_CH[(8*x)+7] … WSEL_CH[8*x] Each such nibble (WSEL_CHx) has positional correspondence to num_intch parameter (each channel has a 1:1 nibble correspondence), so each word ICWSELRx corresponds to eight internal channels for a total of twelve 32-bit registers covering all 96 internal channels.
Page 789: Table 396. Icaworr0–Icaworr2 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Parameter num_intch vector has positional inference for registers ICWER0–2, such that: • num_intch(i) (i = 0–31) corresponds to ICWER0 bit[0:31] • num_intch(i) (i = 32–63) corresponds to ICWER1 bit[0:31] • num_intch(i) (i = 64–95) corresponds to ICWER2 bit[0:31] If any num_intch(i) value is ‘0’, the corresponding bit is not implemented and read access returns ‘0’...
Page 790: Table 398. Tcipr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Parameter num_intch vector has positional inference for registers ICAWORR0–2, such that: • num_intch(i) (i = 0–31) corresponds to ICAWORR0 bit [0:31]. • num_intch(i) (i = 32–63) corresponds to ICAWORR1 bit [0:31]. • num_intch(i) (i = 64–95) corresponds to ICAWORR2 bit [0:31].
Page 791: Table 400. Tcimr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.5.1.22 Test Channel Interrupt Mask Register (TCIMR) The interrupt mask register to channel association is described in Table 401. Offset 0x404 Access: User Read/Write IM_CH[x] Reset IM_CH[x] Reset Figure 350. Test Channel Interrupt Mask Register (TCIMR) Table 400.
Page 792: Table 402. Tcdsr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Offset 0x408 Access: User Read/Write DS_CH[x] Reset DS_CH[x] Reset Figure 351. Test Channel DMA Select Register (TCDSR) Table 402. TCDSR field descriptions Field Description DMA select for channel x 0–31 0 CH[x] is disabled to transfer data in DMA mode. DS_CH[x] 1 CH[x] is enabled to transfer data in DMA mode.
Page 793: Table 404. Tcncmr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Table 404. TCNCMR field descriptions Field Description Normal conversion enable for channel x 0–31 0 Normal conversion is disabled for CH[x]. NCE_CH[x] 1 Normal conversion is enabled for CH[x]. Table 405. Test Channel Normal Conversion Mask Register to Channel Association Register Register bits 31:0 TCNCMR...
Page 794: Table 408. Tcwselr0–Tcwselr3 Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Parameter num_testch vector has positional inference for registers such that num_testch(i) (i = 0–31) corresponds to TCJCMR bit[0:31]. If any of the num_testch(i) value is ‘0’, the corresponding bit is not implemented and read access returns ‘0’ on that bit location. If the complete num_testch is all 0’s, TCJCMR is not implemented and treated as reserved space.
Page 795: Table 410. Tcwenr Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- The number of bits implemented for each WSEL_CHx depends on num_watchdog parameter: • If num_watchdog > 8, the number of bits implemented is 4 (WSEL_CHx[3:0]) • If 4 < num_watchdog <= 8, the number of bits implemented is 3 (WSEL_CHx[3] is reserved).
Page 796: Table 412. Tcaworr Field Descriptions
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Parameter num_testch vector has positional inference for registers TCWENR such that num_testch(i) (i = 0–31) corresponds to TCWENR bit[0:31]. If any of the num_testch(i) value is ‘0’, the corresponding bit is not implemented and read access returns ‘0’ on that bit location.
Page 797: Scriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- 36.5.1.29 Test Channel Connection with Analog Pin Registers 0–7 (TCCAPR0– TCCAPR7) Each test channel can be shorted with any internal analog channel using the configuration programmed in these registers. Test channel short registers to channel association is described in Table 415.
Page 798 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Parameter num_testch vector has positional inference for registers TCCAPRx, such that: • num_testch(i) (i = 0–3) corresponds to TCCAPR0. • num_testch(i) (i = 4–7) corresponds to TCCAPR1. • • num_testch(i) (i = 28–31) corresponds to TCCAPR7. If all the num_testch values in a TCCAPR are ‘0’, the TCCAPR word is not implemented and treated as reserved space.
Page 799: Table 416. Tcdr96–Tcdr127 Field Descriptions
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Offset 0x450–0x4CC Access: User Read/Write Reset CDATA[15:0] Reset Figure 358. Test Channel Data Registers (TCDR96–TCDR127) Table 416. TCDR96–TCDR127 field descriptions Field Description Reserved Write of any value has no effect; read value is always 0. Reference selection This bit can be used to select the reference voltage for channel conversion.
Page 800: Start Of Conversion Pulse Delay
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 416. TCDR96–TCDR127 field descriptions(Continued) Field Description Data overwritten flag This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]: –...
Page 801: Table 417. Start Of Conversion Pulse Delay Table
RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Table 417. Start of conversion pulse delay table Inter domain ADC state Inter domain Register control Trigger source synchronization machine synchronization Comments (ipg_clk_s) (ipg_clk) (ipg_clk_adc) (ipg_clk_adc) Normal Cumulative delay from conversion wen(byte_en) assertion to triggered by —...
Page 802: Initialization Information
Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface Table 417. Start of conversion pulse delay table(Continued) Inter domain ADC state Inter domain Register control Trigger source synchronization machine synchronization Comments (ipg_clk_s) (ipg_clk) (ipg_clk_adc) (ipg_clk_adc) Delay from EOC of last injected channel and adc_start pulse of next 0 (from EOC of injected channel.
Page 803 RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter- Program the PDEDR register with appropriate power down exit delay value. Exit the power down mode by clearing the MCR[PWDN] bit. After the power down mode is exited the SARADC enters the IDLE state, this can be checked by polling for MSR[ADCSTATUS] bits.
Page 804: Introduction
Decimation Filter RM0400 Decimation Filter 37.1 Introduction This chapter describes the Decimation Filter block. 37.1.1 Overview The decimation filter is a dedicated hardware block, designed to decimate fixed point sample conversion results. An interface is provided for use by the CPU, allowing setup of the filter parameters and read/write of the configuration registers and filter samples.
Page 805: Figure 359. Decimation Filter Block Diagram
RM0400 Decimation Filter Figure 359. Decimation Filter Block Diagram Device Slave-Bus Line Counter Control Decoder Enable/Clear Logic Counter Tx En Sample/ By-pass Select Control MAC Done Select Field done Coefficient Coefficient data-in 1 Cascade Register File Data Decimated Output Sample Decimated Result Clear/Load...
Page 806: Features
Decimation Filter RM0400 37.1.2 Features The Decimation Filter block includes these distinctive features: • Selectable 4th order IIR filter, or an 8th order FIR filter – Input/output with 16-bit (fixed point) two’s complement signed values – Internal taps with 16-bit (feed-forward portion of first IIR) and 24-bit (feedback portion) resolutions (fixed point) for two’s complement signed value –...
Page 807: External Signal Description
RM0400 Decimation Filter in the Output Buffer register. The filter output is also consumed by a CPU or DMA mastering the same device slave-bus interface. This operation mode can be used to debug the filter stability or to decimate data in System RAM. 37.1.3.2 Low Power mode Low power mode corresponds to the module disable mode or stop mode.
Page 808: Decimation Filter Device Memory Map
Decimation Filter RM0400 37.3.1 Decimation filter device memory map The addresses of the Decimation Filter registers are specified as offsets from the module’s base address, described in Table 419. The registers allocated in this memory map are sufficient for a 4th order IIR filter implementation. Table 419.
Page 809: Decimation Filter Register Descriptions
RM0400 Decimation Filter Table 419. Block memory map(Continued) Reset Address offset Register Access Section/Page Value 0x0000_ 0x078 DECFILTER_TAP0 — Filter TAP 0 Register 0000 0x0000_ 0x07C DECFILTER_TAP1 — Filter TAP 1 Register 0000 0x0000_ 0x080 DECFILTER_TAP2 — Filter TAP 2 Register 0000 0x0000_ 0x084...
Page 810: Table 420. Decfilter_Mcr Field Descriptions
Decimation Filter RM0400 Address: DECFILTER_BASE + 0x000 Access: User read/write MDIS IDEN FTYPE[1:0] SCAL[1:0] Reset — IDIS SAT ISEL DEC_RATE[3:0] SDIE IBIE OBIE Reset Reset value is defined by the MDIS_DEFAULT parameter value. Figure 360. Decimation Filter Module Configuration Register (DECFILTER_MCR) Table 420.
Page 811 RM0400 Decimation Filter Table 420. DECFILTER_MCR field descriptions(Continued) Field Description Input Data Interrupt Enable The IDEN bit enables the Decimation Filter to generate interrupt requests on all new input data written to the Interface Input Buffer register or Input/Output Buffers register. IDEN 1 Input Data Interrupt Enabled 0 Input Data Interrupt Disabled...
Page 812 Decimation Filter RM0400 Table 420. DECFILTER_MCR field descriptions(Continued) Field Description Saturation Enable The SAT bit enables the saturation of the filter output. See Section 37.4.6.2: Saturation, for more details. 0 Enable Saturation 1 Disable Saturation Input Selection The ISEL bit selects the source of input data to the Filter. The data source is the CPU/DMA on the device slave-bus interface.
Page 813: Table 421. Decfilter_Mcr Field Descriptions
RM0400 Decimation Filter 37.3.2.2 Decimation Filter Module Status Register (DECFILTER_MSR) Address: DECFILTER_BASE + 0x004 Access: User read/write R BSY DEC_COUNTER[3:0] IDFC IBIC OBIC IVRC Reset IBIF OBIF OVF OVR IVR Reset Figure 361. Decimation Filter Status Register (DECFILTER_MSR) Table 421. DECFILTER_MCR field descriptions Field Description Decimation Filter Busy indication...
Page 814 Decimation Filter RM0400 Table 421. DECFILTER_MCR field descriptions(Continued) Field Description Output Buffer Interrupt Request Clear bit The OBIC bit clears the OBIF Flag bit in the Status Register. This bit is self negated, therefore it is always read as zero. OBIC 0 No action 1 Clears OBIF...
Page 815 RM0400 Decimation Filter Table 421. DECFILTER_MCR field descriptions(Continued) Field Description Input Buffer Interrupt Request Flag The IBIF bit flag indicates that the input buffer DECFILTER_IB is available to be filled with new data, when Enhanced Debug Monitor is off. In Enhanced Debug Monitor, it indicates the input buffer DECFILTER_IB was filled with a new sample and is ready to be read.
Page 816: Table 422. Decfilter_Mxcr Field Descriptions
Decimation Filter RM0400 37.3.2.3 Decimation Filter Module Extended Configuration Register (DECFILTER_MXCR) Address DECFILTER_BASE + 0x008 Access: User read/write SSIG Reset SZROSEL SHLTSEL SRQSEL SENSEL Reset Figure 362. Decimation Filter Extended Configuration Register (DECFILTER_MXCR) Table 422. DECFILTER_MXCR field descriptions Field Description Integrator DMA Enable The SDMAE bit enables the DMA request when an integrator output is requested (see Section 37.4.13.2: Integrator...
Page 817 RM0400 Decimation Filter Table 422. DECFILTER_MXCR field descriptions(Continued) Field Description Integrator Output Request The SRQ bit is used to command the update of the integrator output, reflected in the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT. It may also cause a DMA or interrupt request, depending on the DECFILTER_MCR bit SDIE and DECFILTER_MXCR bit SDMAE.
Page 818: Figure 363. Decimation Filter Extended Status Register (Decfilter_Mxsr)
Decimation Filter RM0400 Table 422. DECFILTER_MXCR field descriptions(Continued) Field Description Integrator Output Read Request Mode Selection The SRQSEL field defines the use of the integrator output request hardware input signal, according to the parameters below. An integrator output request updates the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT, also causing a DMA or interrupt request.
Page 819: Table 423. Decfilter_Mxsr Field Descriptions
RM0400 Decimation Filter Table 423. DECFILTER_MXSR field descriptions Field Description Reserved Integrator Output Data Flag Clear bit The SDFC bit clears the SDF Flag bit in the Status Register. This bit is self negated, therefore it is always read as zero. SDFC 0 No action 1 Clears SDF...
Page 820 Decimation Filter RM0400 Table 423. DECFILTER_MXSR field descriptions(Continued) Field Description Integrator Sum Exception flag The SSE bit indicates an exceptional condition of the integrator accumulator. This flag generates an Interrupt Request if enabled by the DECFILTER_MCR bit ERREN, and it is cleared by the SSEC bit or by a soft reset.
Page 821: Table 424. Decfilter_Ib Field Descriptions
RM0400 Decimation Filter 37.3.2.5 Decimation Filter Interface Input Buffer register (DECFILTER_IB) The Input Buffer Register provides access to the Input buffer of the decimation filter when the filter is in the standalone mode of operation. Writes to this register are interpreted as requests to the Decimation Filter to process new sample data.
Page 822: Table 425. Decfilter_Ob Field Descriptions
Decimation Filter RM0400 37.3.2.6 Decimation Filter Interface Output Buffer register (DECFILTER_OB) Address: DECFILTER_BASE + 0x014 Access: User read only OUTTAG[3:0] Reset OUTBUF[15:0] Reset Figure 365. Decimation Filter Interface Output Buffer register (DECFILTER_OB) Table 425. DECFILTER_OB field descriptions Field Description 0-10 Reserved Reserved Decimation filter output tag bits...
Page 823: Table 426. Decfilter_Coefn Field Descriptions
RM0400 Decimation Filter Table 426. DECFILTER_COEFn field descriptions Field Description Coefficient n field The COEFn[23:0] bit fields are the digital filter coefficients registers. The coefficients are fractional signed values in two’s complement format, in the range (-1 ≤ coef < 1). 8-31 COEFn[23:0] Note: Reads to this register are sign-extended, meaning the coefficient’s sign bit is copied to all 8...
Page 824: Table 428. Decfilter_Fintval Field Descriptions
Decimation Filter RM0400 37.3.2.9 Decimation Filter Final Integration Value register (DECFILTER_FINTVAL) Address: DECFILTER_BASE + 0x0E0 Access: User read only SUM_VALUE[31:16] Reset SUM_VALUE[15:0] Reset Figure 368. Decimation Filter Final Integration Value register (DECFILTER_FINTVAL) Table 428. DECFILTER_FINTVAL field descriptions Field Description Integration Sum Value The SUM_VALUE[31:0] field holds the sum of filtered output values.
Page 825: Table 429. Decfilter_Fintcnt Field Descriptions
RM0400 Decimation Filter 37.3.2.10 Decimation Filter Final Integration Count Value register (DECFILTER_FINTCNT) Address: DECFILTER_BASE + 0x0E4 Access: User read only COUNT[31:16] Reset COUNT[15:0] Reset Figure 369. Decimation Filter Final Integration Count Value register (DECFILTER_FINTCNT) Table 429. DECFILTER_FINTCNT field descriptions Field Description Integration Count Value The COUNT field holds the count of filtered outputs integrated.
Page 826: Functional Description
Decimation Filter RM0400 Table 430. DECFILTER_CINTVAL field descriptions Field Description Integration Sum Value The SUM_VALUE[31:0] field holds an unsigned number representing the sum of filtered output values, continuously updated as the integration proceeds. The control of the integration sum is determined by the register DECFILTER_MXCR (see <Cross Refs>Section 37.3.2.3, “Decimation Filter Module Extended Configuration Register (DECFILTER_MXCR)”).
Page 827: Data Interface Sub-Block Description
RM0400 Decimation Filter modules, transmitter and receiver, that are accessed by the slave-bus interface. The bypass path is used when the filter is disabled and the incoming data can be transmitted back to the master block without being processed by the Filter algorithm. The Filter hardware is implemented in such a way that an IIR (1 x 4 poles) or FIR filter type can be implemented.
Page 828: Output Buffer Description
Decimation Filter RM0400 The input buffer overrun can occur only when the input is enabled (DECFILTER_MCR bit IDIS=0). 37.4.4 Output buffer description The decimation filter has an output buffer to send filtering results to the CPU using the device slave-bus, as selected through the DECFILTER_MCR bits ISEL. Filtering of prefill inputs do not update the output buffer, so the flag ODF is not set.
Page 829: Iir And Fir Filter
RM0400 Decimation Filter output with no change. This behavior is independent of the ISEL setting. The following applies to the bypass configuration: • flush is ignored • prefill is ignored • counted decimation is ignored • BSY bit is not set •...
Page 830: Figure 373. Fourth Order Iir Filter Implementation Block Diagram
Decimation Filter RM0400 Equation 19       y n ( ) ---- - x n i – ---- - y n j –       Where all the coefficients are scaled down by S. The block diagram for Equation 19 shown in Figure 373...
Page 831: Figure 374. Filter Configuration Paths (Fir Or 1X4Poles Iir)
RM0400 Decimation Filter Figure 374. Filter Configuration Paths (FIR or 1x4Poles IIR) y(n) Scale Factor S Round/Sat x(n) Register Coefficient 0 Round/Sat FTYPE[1:0] Tap0 Coefficient 1 Coefficient 5 Tap4 FIR Section IIR Section Tap1 Coefficient 2 Coefficient 6 Tap5 Tap2 Coefficient 3 Coefficient 7 Tap6...
Page 832: Filter Prefill Control Description
Decimation Filter RM0400 Figure 375. Convergent Rounding Methodology MS_WORD LS_WORD xx...xx xx..xx..00100 1000..00..00 Before Rounding xx...xx xx..xx..00100 Rounded Down xx...xx xx..xx..001 1000..00..00 Before Rounding xx...xx xx..xx..00110 Rounded Up 37.4.6.2 Saturation Filter output saturation occurs when an overflow or underflow condition of the filter is detected by dedicated logic, and if it is enabled by the SAT control bit of the configuration register DECFILTER_MCR.
Page 833: Soft Reset Command Description
RM0400 Decimation Filter When the flush control is detected, all filter TAPs are cleared and the DEC_COUNTER[3:0] field in the status register DECFILTER_MSR is reset. The flush function does not clear the Coefficient registers file in the Decimation Filter, thus it is not required to re-write these registers after a flush.
Page 834: Interrupts Requests Description
Decimation Filter RM0400 37.4.10 Interrupts requests description 37.4.10.1 Block interrupt request There are several interrupt request events that can be enabled using the module configuration register DECFILTER_MCR. Basically, the interrupt request can be issued under any of the following conditions: •...
Page 835: Dma Requests Description
RM0400 Decimation Filter 37.4.10.3 Output buffer interrupt request This interrupt is enabled by the register OBIE in the DECFILTER_MCR register and is asserted only when DSEL=0. This request is also indicated in the field OBIF of the DECFILTER_MSR register. When in standalone mode, the output buffer can be read by the CPU with the DMA disabled.
Page 836: Integrator
Decimation Filter RM0400 Access to input and output buffers remain operational in freeze, as well as their related flags. 37.4.13 Integrator The hardware sample integrator accumulates the filter output values for determined periods. 37.4.13.1 Integrator inputs The integrator can be fed either by raw or decimated filter outputs, selected by the DECFILTER_MXCR bit SISEL (see Section 37.3.2.3: Decimation Filter Module Extended Configuration Register...
Page 837 RM0400 Decimation Filter The integrator output request also updates the register DECFILTER_FINTCNT, which holds the number of samples accumulated into the register DECFILTER_FINTVAL. This internal accumulated sample counter can operate either in a saturated or “wrapped” count mode, as selected by the DECFILTER_MXCR bit SCSAT. In both cases, the counter overflow is flagged by the DECFILTER_MXSR bit SCOVF.
Page 838 Decimation Filter RM0400 integrator registers immediately. Integrator zero command from external signal or by software (SZRO) affects the integrator registers and flags as follows: • DECFILTER_CINTVAL resets immediately; • DECFILTER_CINTCNT does not reset immediately; it is updated only upon a DECFILTER_CINTVAL read, loaded with the number of integrated samples occurred after the reset;...
Page 839: Initialization Information
RM0400 Decimation Filter The accumulator exception condition depends on whether or not it operates in saturated mode as follows: • In Saturated operation (DECFILTER_MXCR bit SSAT=1): a sum exception occurs (SSE=1) whenever an overflow is flagged; SSE asserts together with SSOVF. •...
Page 840: Filter Example Simulation
Decimation Filter RM0400 37.6 Filter example simulation The decimation filter block operation was checked in a Verilog simulation using calculated filter coefficient values and noisy input data. The expected output values and the RMS error were then calculated. 37.6.1 Coefficients calculation The coefficients were calculated using a digital filter design tool.
Page 841: Input Data Calculation
RM0400 Decimation Filter Table 433. Coefficient values for decimation filter SCALE Hexadecimal Values COEFn Decimal Value Decimal Value (24 bits) Coef0 = B0/S 0.0221455 0.00276815891266 0x005AB5 Coef1 = B1/S 0.00445582948893748 0.00055694580078 0x001240 Coef2 = B2/S 0.0318517846509088 0.00398147106171 0x008277 Coef3 = B3/S 0.00445582948893748 0.00055694580078 0x001240...
Page 842: Temperature Sensor
Temperature Sensor RM0400 Temperature Sensor 38.1 Introduction The device includes two on-chip temperature sensors that monitor device temperature and delivers one analog output signal and three digital output signals each. The analog output consists of a voltage signal directly proportional to the internal junction temperature. The analog output is connected to an input channel of an ADC on the device.
Page 843: Linear Temperature Sensor (Analog Output Generation)
RM0400 Temperature Sensor When the temperature threshold detection feature is enabled , the temperature sensor monitors the internal junction temperature of the chip and asserts a signal if any of the three specified temperature thresholds are crossed. • The low temperature digital output signals if the junction temperature falls below the low temperature threshold (–40 °C).
Page 844: Temperature Formula
Temperature Sensor RM0400 linear voltage-temperature relation with coefficients adjusted by calibration parameters extracted during factory test and programmed into flash memory. 38.3 Temperature formula The system chain that translates device junction temperature into a digital variable is comprised of the temperature sensor, a reference voltage source and the on-chip ADC. Both analog output voltages of the temperature sensor and the reference voltage source must be converted by the ADC into digital codes to obtain the device junction temperature.
Page 845: Calculating Device Temperature
RM0400 Temperature Sensor shows how parameters TSCA and TSCB are calculated in terms of the actual variables measured during factory calibration. The calibration points are illustrated in Figure 378. Figure 378. Calibration Points FINAL JUNCTION FINAL TSENS TSENS HIGH TSENS JUNCTION HIGH 38.4...
Page 846: System Timer Module (Stm)
System Timer Module (STM) RM0400 System Timer Module (STM) 39.1 Introduction 39.1.1 Overview The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel.
Page 847: Register Descriptions
RM0400 System Timer Module (STM) Table 434. STM memory map(Continued) Address offset Register Location 0x0010 STM Channel 0 Control Register (STM_CCR0) on page 848 0x0014 STM Channel 0 Interrupt Register (STM_CIR0) on page 849 0x0018 STM Channel 0 Compare Register (STM_CMP0) on page 849 0x001C Reserved...
Page 848: Table 435. Stm_Cr Field Descriptions
System Timer Module (STM) RM0400 Table 435. STM_CR field descriptions Field Description Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256). 0x00 Divide system clock by 1 16:23 0x01 Divide system clock by 2 0xFF Divide system clock by 256 Freeze.
Page 849: Table 437. Stm_Ccrn Field Descriptions
RM0400 System Timer Module (STM) Offset: 0x10+0x10*n Access: Read/Write Reset Reset Figure 381. STM Channel Control Register (STM_CCRn) Table 437. STM_CCRn field descriptions Field Description Channel Enable. 0 The channel is disabled. 1 The channel is enabled. 39.3.2.4 STM Channel Interrupt Register (STM_CIRn) The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
Page 850: Functional Description
System Timer Module (STM) RM0400 Offset: 0x18+0x10*n Access: Read/Write 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 383.
Page 851: Software Watchdog Timer (Swt)
RM0400 Software Watchdog Timer (SWT) Software Watchdog Timer (SWT) 40.1 Introduction 40.1.1 Overview The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate.
Page 852: Register Descriptions
Software Watchdog Timer (SWT) RM0400 SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO, SWT_WN, and SWT_SK registers are read-only. The SWT memory map is shown in Table 440. The reset values of SWT_CR and SWT_TO are device specific. These values are determined by SWT inputs. Table 440.
Page 853: Table 441. Swt_Cr Field Descriptions
RM0400 Software Watchdog Timer (SWT) Table 441. SWT_CR field descriptions Field Name Description Master Access Protection for Master n. The platform bus master assignments are device specific. Not all MAPn fields are implemented. See the device configuration section for master ports MAPn that are implemented on the crossbar switch.
Page 854: Table 442. Swt_Ir Field Descriptions
Software Watchdog Timer (SWT) RM0400 40.3.1.2 SWT Interrupt Register (SWT_IR) The SWT_IR contains the time-out interrupt flag. 0x0004 Offset Access: Read/Write Reset Reset Figure 385. SWT Interrupt Register (SWT_IR) Table 442. SWT_IR field descriptions Field Name Description Time-out Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect.
Page 855: Table 443. Swt_To Field Descriptions
RM0400 Software Watchdog Timer (SWT) Table 443. SWT_TO field descriptions Field Name Description Watchdog time-out period in clock cycles. An internal 32-bit down counter is loaded with this value when the service sequence is written or when the SWT is enabled. 0-31 The initial value is 0x0003_FDE0.
Page 856: Table 445. Swt_Sr Field Descriptions
Software Watchdog Timer (SWT) RM0400 Table 445. SWT_SR field descriptions Field Name Description Watchdog Service Code.This field is used to service the watchdog and to clear the soft lock bit (SWT_CR[SLK]). If the SWT_CR[KEY] bit is set, two pseudorandom key values are written to service the watchdog, see Section <Cross Refs>40.3.1.1 for details.
Page 857: Functional Description
RM0400 Software Watchdog Timer (SWT) Table 447. SWT_SK field descriptions Field Name Description Service Key.This field is the previous (or initial) service key value used in keyed service mode. If 16-31 SWT_CR[KEY] is set, the next key value to be written to the SWT_SR is (17*SK+3) mod 2 40.4 Functional description The SWT is a 32-bit timer designed to enable the system to recover in situations such as...
Page 858: Figure 391. Pseudorandom Key Generator
Software Watchdog Timer (SWT) RM0400 example, if SWT_SK[SK] is 0x0100, then the service sequence keys are 0x1103, 0x2136. In this mode, each time a valid key is written to the SWT_SR register, the SWT_SK register is updated. So, after servicing the watchdog by writing 0x1103 and then 0x2136 to the SWT_SR[WSC] field, SWT_SK[SK] is 0x2136 and the next key sequence is 0x3499, 0x7E2C.
Page 859: Periodic Interrupt Timer (Pit)
RM0400 Periodic Interrupt Timer (PIT) Periodic Interrupt Timer (PIT) 41.1 Introduction The PIT timer module is an array of timers that can be used to raise interrupts and trigger DMA channels. Note: For the chip-specific implementation details of this module’s instances see the Device Configuration chapter.
Page 860: Features
Periodic Interrupt Timer (PIT) RM0400 41.1.2 Features The main features of this block are: • Timers can generate DMA trigger pulses • Timers can generate interrupts • All interrupts are maskable • Independent timeout periods for each timer 41.2 Signal description This module has no external pins.
Page 861: Figure 393. Pit Module Control Register (Pitx_Mcr)
RM0400 Periodic Interrupt Timer (PIT) Table 448. PITx memory map(Continued) Offset Width Register name Access Location (hex) (bits) 0000_0138 PIT Timer Control Register 3 (PITx_TCTRL3) on page 864 0000_013C PIT Timer Flag Register 3 (PITx_TFLG3) on page 865 0000_0140 PIT Timer Load Value Register 4 (PITx_LDVAL4) on page 863 0000_0144 PIT Current Timer Value Register 4 (PITx_CVAL4)
Page 862: Table 449. Pitx_Mcr Field Descriptions
Periodic Interrupt Timer (PIT) RM0400 Table 449. PITx_MCR field descriptions Field Description 0–29 This read-only bitfield is reserved and always has the value zero. Reserved Module Disable This is used to disable the module clock. This bit must be enabled before any other setup is done.
Page 863: Table 451. Pitx_Ltmr64L Field Descriptions
RM0400 Periodic Interrupt Timer (PIT) the first access, therefore the application does not need to worry about carry-over effects of the running counter. Address Base + 0x00E4 Access: User read-only Reset Reset Figure 395. PIT Lower Lifetime Timer Register (PITx_LTMR64L) Table 451.
Page 864: Table 453. Pitx_Cvaln Field Descriptions
Periodic Interrupt Timer (PIT) RM0400 41.2.1.5 PIT Module x Current Timer Value Register n (PITx_CVALn) Address: Base + 0x0104 Access: User read-only Reset Reset Figure 397. PIT Module x Current Timer Value Register n (PITx_CVALn) Table 453. PITx_CVALn field descriptions Field Description Current Timer Value...
Page 865: Table 454. Pitx_Tctrln Field Descriptions
RM0400 Periodic Interrupt Timer (PIT) Table 454. PITx_TCTRLn field descriptions Field Description 0–28 This read-only bitfield is reserved and always has the value zero. Reserved Chain Mode Bit When activated, timer n-1 needs to expire before timer n can decrement by 1. Timer 0 cannot be changed.
Page 866: Functional Description
Periodic Interrupt Timer (PIT) RM0400 41.3 Functional description This section provides the functional description of the module. 41.3.1 General This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses as well as to generate interrupts. Each interrupt is available on a separate interrupt line.
Page 867: Interrupts
RM0400 Periodic Interrupt Timer (PIT) Figure 402. Dynamically setting a new load value Timer Enabled New Start Start Value = p1 Value p2 set Trigger Event 41.3.1.2 Debug mode In debug mode, the timers will be frozen based on field PITx_MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (for example, the timer values) and then continue the operation.
Page 868: Example Configuration For Chained Timers
Periodic Interrupt Timer (PIT) RM0400 Timer 3 shall be used only for triggering. Therefore Timer 3 is started by writing a ‘1’ to bit TCTRL3[TEN]; bit TIE stays at 0. The following example code matches the described setup: Example 18. // turn on PIT PIT_MCR = 0x00;...
Page 869: Example Configuration For The Lifetime Timer
RM0400 Periodic Interrupt Timer (PIT) // Timer 1 PIT_LDVAL1 = 0x23C345FF; // setup timer 1 for 600 000 000 cycles PIPIT_TCTRL1 = TEN; // start timer 1 41.6 Example Configuration for the Lifetime Timer To configure the life timer, channels 0 and 1 need to be chained together. First the PIT module needs to be activated by writing a ‘0’...
Page 870: Gtm Development Interface (Gtmdi)
GTM Development Interface (GTMDI) RM0400 GTM Development Interface (GTMDI) 42.1 About this module The GTMDI debug module unit is a hardware module that: • Monitors the software and hardware activities of GTM-IP • Reads the registers without interfering with the logic status, even for FIFOs, by configuring the debug access controls 42.2 Introduction...
Page 871: Overview
RM0400 GTM Development Interface (GTMDI) Figure 403. GTMDI block diagram Global Time Timestamp Start/stop Stamp trace control Message Data Trace Data Bus Req Level Fetch Trace Data Valid WPT Trace Not Empty WPT Trace Event Queue WPT Trace ATOM WPT Trace WPT Trace Ready DPLL...
Page 872: Figure 404. Gtmdi And Gtm Interface
GTM Development Interface (GTMDI) RM0400 implement complex debug features. Trace capability is also provided along with a global time-stamp which allows real time trace for several GTM sub-module events. The GTMDI implements a Nexus Client standard interface and a JTAG standard Port Controller to provide communication capability with the JTAG and NAR on-chip modules.
Page 873: Table 456. Gtm Sub-Module Instances
RM0400 GTM Development Interface (GTMDI) Table 456. GTM Sub-module instances Module Number of instances ATOM numMCS Figure 405 shows the Watchpoint Triggers (WPT) and Watchpoint Messages (WPM). Each GTM sub-module generates two watchpoints which can be routed internally to the GTMDI and generate watchpoint triggers or routed to the message formatter and generate watchpoint messages.
Page 874: Figure 405. Watchpoint Triggers And Watchpoint Messages
GTM Development Interface (GTMDI) RM0400 Figure 405. Watchpoint triggers and watchpoint messages GTMDI MESSAGES TRIGGERS TIM CH SEL 1/2 TOM CH SEL 1/2 ATOM CH SEL 1/2 SPEA SEL 1/2 SPEB SEL 1/2 ARU CH SEL client interface TBU0 SEL TBU1 SEL TBU2 SEL Start/stop...
Page 875: Features
RM0400 GTM Development Interface (GTMDI) 42.3.1 Features The GTMDI block implements the following features: • Full duplex pin interface for medium and high visibility throughput – 2 EVTO (Event Out) for GTM real time signal monitoring – 1 EVTI (Event In) –...
Page 876: Modes Of Operation
GTM Development Interface (GTMDI) RM0400 42.3.2 Modes of operation The GTMDI block is placed in reset when the Nexus reset signal is asserted. The JTAG registers controlled by the TCK clock are also put into the reset state if the TAP controller is in the TEST-LOGIC-RESET state.
Page 877: Event In (Evti)
RM0400 GTM Development Interface (GTMDI) Table 457. GTMDI signal properties Name Port Function Reset State EVTI Auxiliary Event In pin — EVTO[1:0] Auxiliary Event Out pin [11] Test Clock Input — Test Data Input — Test Data Output Test Mode Select Input —...
Page 878: Test Mode Select (Tms)
GTM Development Interface (GTMDI) RM0400 42.4.6 Test Mode Select (TMS) Test Mode Select (TMS) is an input pin used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCK. 42.5 Register definition This section provides a detailed description of all GTMDI registers accessible to the development tool.
Page 879 RM0400 GTM Development Interface (GTMDI) Table 458. GTMDI registers(Continued) Register Index Read/write Reserved 47–49 — ARU Watchpoint Control (GTMDI_ARU_WPC1) ARU Watchpoint Control (GTMDI_ARU_WPC2) ARU DATA0H (GTMDI_ARU_DATA0H) ARU DATA0L (GTMDI_ARU_DATA0L) ARU DATA1H (GTMDI_ARU_DATA1H) ARU DATA1L (GTMDI_ARU_DATA1L) ARU Data Trace Control (GTMDI_ARU_DTC) Reserved 57–59 —...
Page 880: Register Descriptions
GTM Development Interface (GTMDI) RM0400 Table 458. GTMDI registers(Continued) Register Index Read/write MCSB Data Trace Address Range 2 (GTMDI_MCSB_DTAR2) Reserved 90–93 — TBU0 Watchpoint Control 1 (GTMDI_TBU0_WPC1) TBU0 Watchpoint Control 2 (GTMDI_TBU0_WPC2) TBU0 DATA (GTMDI_TBU0_DATA) Reserved 97–100 — TBU1 Watchpoint Control 1 (GTMDI_TBU1_WPC1) TBU1 Watchpoint Control 2 (GTMDI_TBU1_WPC2) TBU1 DATA (GTMDI_TBU1_DATA) Reserved...
Page 881: Table 459. Did Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 459. DID field descriptions Field Description 31–28 Part Revision Number. Contains the revision number of the part. 27–22 Design Center. Indicates the design center. 21–12 Part Identification Number. Contains the part number of the device. Value is PIN 11–1 Manufacturer Identity Code.
Page 882: Table 460. Gtmdi_Dc Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 460. GTMDI_DC field descriptions Field Description Global Debug Enable. This control bit disables all debug features of the GTMDI module including ability to put GTM IP in Halt state, modify EVTO output, send messages to the DATA bus and set triggers to the SPU module.
Page 883 RM0400 GTM Development Interface (GTMDI) Table 460. GTMDI_DC field descriptions(Continued) Field Description Clear Halt Request. Writing this bit to one clears halt requests., which means GTM resumes normal operation out of halt state. The status bits of the GTMDI_DS register are cleared. This bit is self- cleared thus read always as zero.
Page 884: Table 461. Gtmdi_Ds Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 6 RESET: RESET: Figure 408. GTMDI development status register (GTMDI_DS) Table 461 describes the GTMDI_DS register functions. Note: The HS1 and HS2 bit fields are cleared as soon as the GTM resumes normal operation which is controlled by the CHR bit in the GTMDI_DC register.
Page 885 RM0400 GTM Development Interface (GTMDI) Table 461. GTMDI_DS field descriptions(Continued) Field Description Stop Status. Indicates if the GTM is in stop mode with no active clocks. Besides the system level stop mode mechanism, the GTM may independently be programmed for STOP mode by setting the Module Disable Control bit.
Page 886: Table 462. Gtmdi_Tim_Wpc1 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 11 TSS1 SSEL1 HEN1 WMC1 CHSEL1 RESET: TSS2 SSEL2 HEN2 WMC2 CHSEL2 RESET: Figure 409. TIM watchpoint control 1 register (GTMDI_TIM_WPC1) Table 462 describes the GTMDI_TIM_WPC1 register functions. Table 462. GTMDI_TIM_WPC1 field descriptions Field Description TIM Channel Slope Selection 1.
Page 887 RM0400 GTM Development Interface (GTMDI) Table 462. GTMDI_TIM_WPC1 field descriptions(Continued) Field Description TIM channel selection 1. Selects which channel within a selected TIM sub-module generates watchpoints. The selection is actually on the TIM channel input filter. 000 TIM CH0 001 TIM CH1 18–16 010 TIM CH2 CHSEL1...
Page 888: Table 463. Gtmdi_Tim_Wpc2 Field Descriptions
GTM Development Interface (GTMDI) RM0400 42.5.1.5 TIM watchpoint control register 2 (GTMDI_TIM_WPC2) The GTMDI_TIM_WPC2 register shown in Figure 410 controls the Watchpoint Triggers WPT issued by TIM channels. These watchpoint triggers are used to control GTM Halt state entering, watchpoint messages and control external logic to the GTMDI. See Figure 453 details of the logic that uses the bits in this register.
Page 889 RM0400 GTM Development Interface (GTMDI) Table 463. GTMDI_TIM_WPC2 field descriptions(Continued) Field Description Start/Stop Enable 1. The SEN1 bit field enables the selected TIM channel to consider the Start/Stop inputs for watchpoint trace messages control. If this bit is cleared, the messages are controlled only by JTAG writes to the WMC1 field in the GTMDI_TIM_WPC1 register.
Page 890: Table 464. Gtmdi_Tom_Wpc1 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 17 TSS1 SSEL1 HEN1 WMC1 CHSEL1 RESET: TSS2 SSEL2 HEN2 WMC2 CHSEL2 RESET: Figure 411. TOM watchpoint control 1 register (GTMDI_TOM_WPC1) Table 464 describes the GTMDI_TOM_WPC1 register functions. Table 464. GTMDI_TOM_WPC1 field descriptions Field Description TOM Channel Slope Selection 1.
Page 891 RM0400 GTM Development Interface (GTMDI) Table 464. GTMDI_TOM_WPC1 field descriptions(Continued) Field Description TOM channel selection 1. Selects which channel within a selected TOM sub-module generates watchpoints. 0000 TOM CH0 0001 TOM CH1 0010 TOM CH2 0011 TOM CH3 0100 TOM CH4 0101 TOM CH5 19–16 0110 TOM CH6...
Page 892: Figure 412. Tom Watchpoint Control 2 Register (Gtmdi_Tom_Wpc2)
GTM Development Interface (GTMDI) RM0400 Table 464. GTMDI_TOM_WPC1 field descriptions(Continued) Field Description Watchpoint Message Control 2. The WMC2 Watchpoint Message Control 2 bit controls the watchpoint message sent through the Message Data bus. If this bit is set it enables valid transitions on the selected TOM Channel output to generate a watchpoint message.
Page 893: Table 465. Gtmdi_Tom_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 465. GTMDI_TOM_WPC2 field descriptions Field Description Watchpoint Trigger Output Selection 1. The WTSEL1[2:0] bit field selects among 8 available output Watchpoint triggers which one is connected to the selected TOM Channel. Other modules can select the same WTSEL1 value, in this case the result watchpoint signal implements an OR of all selected sources.
Page 894: Figure 413. Atom Watchpoint Control 1 Register (Gtmdi_Atom_Wpc1)
GTM Development Interface (GTMDI) RM0400 Table 465. GTMDI_TOM_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Enable 2. The TEN2 field controls if a Watchpoint external trigger is issued by the selected TOM channel. TEN2 0 Disable Trigger Generation 1 Enable Trigger Generation Start/Stop Enable 2.
Page 895: Table 466. Gtmdi_Atom_Wpc1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 466. GTMDI_ATOM_WPC1 field descriptions Field Description ATOM Channel Slope Selection 1. The TSS1 field selects the slope for the ATOM selected channel. 00 Any transition (both) 29–28 01 Transition from 0 to 1 (positive slope) TSS1 10 Transition from 1 to zero (negative slope) 11 Reserved...
Page 896 GTM Development Interface (GTMDI) RM0400 Table 466. GTMDI_ATOM_WPC1 field descriptions(Continued) Field Description ATOM sub-module Source Selection 2. Selects which ATOM module is the source for watchpoint generation. 0000 ATOM0 0001 ATOM1 0010 ATOM2 0011 Reserved 0100 Reserved 0101 Reserved 11–8 0110 Reserved SSEL2 0111 Reserved...
Page 897: Table 467. Gtmdi_Atom_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Register index: 24 WTSEL1 STSEL1 TEN1 SEN1 RESET: WTSEL2 STSEL2 TEN2 SEN2 RESET: Figure 414. ATOM watchpoint control 2 register (GTMDI_ATOM_WPC2) Table 467 describes the GTMDI_ATOM_WPC2 register functions. Table 467. GTMDI_ATOM_WPC2 field descriptions Field Description Watchpoint Trigger Output Selection 1.
Page 898 GTM Development Interface (GTMDI) RM0400 Table 467. GTMDI_ATOM_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Output Selection 2. The WTSEL2[2:0] field selects among 8 available Watchpoint trigger outputs which one is connected to the ATOM selected channel. Other modules can selected the same WTSEL2 value, in this case the result signal is an OR of all selected sources.
Page 899: Table 468. Gtmdi_Spea_Wpc1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Register index: 29 SSEL WMC1 TSS1 HEN1 RESET: WMC2 TSS2 HEN2 RESET: Figure 415. SPEA watchpoint control 1 register (GTMDI_SPEA_WPC1) Table 468 describes the GTMDI_SPEA_WPC1 register functions. Table 468. GTMDI_SPEA_WPC1 field descriptions Field Description SPEA sub-module Source Selection. Selects which SPE sub-module is the source for watchpoint generation.
Page 900: Figure 416. Spea Watchpoint Control 2 Register (Gtmdi_Spea_Wpc2)
GTM Development Interface (GTMDI) RM0400 Table 468. GTMDI_SPEA_WPC1 field descriptions(Continued) Field Description SPEA DIR Slope Selection. The TSS2 field selects the slope for the DIR signal. 00 Any transition (both) 5–4 01 Transition from 0 to 1 (positive slope) TSS2 10 Transition from 1 to zero (negative slope) 11 Reserved Halt Enable 2.
Page 901: Table 469. Gtmdi_Spea_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 469. GTMDI_SPEA_WPC2 field descriptions Field Description Watchpoint Trigger Output Selection 1. The WTSEL1[2:0] bit field selects among 8 available watchpoint triggers which one is connected to the NIPD SPEA signal. Other modules can select the same WTSEL1 value, in this case the result watchpoint signal implements an OR of all selected sources.
Page 902: Figure 417. Speb Watchpoint Control 1 Register (Gtmdi_Speb_Wpc1)
GTM Development Interface (GTMDI) RM0400 Table 469. GTMDI_SPEA_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Enable 2. The TEN2 field controls if a watchpoint external trigger is issued by the SPEA DIR selected event. TEN2 0 Disable External Watchpoint Trigger Generation 1 Enable External Watchpoint Trigger Generation Start/Stop Enable 2.
Page 903: Table 470. Gtmdi_Speb_Wpc1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 470. GTMDI_SPEB_WPC1 field descriptions Field Description SPEB sub-module Source Selection . Selects which SPE sub-module is the source for watchpoint generation. 000 SPE1 001 Reserved 26–24 010 Reserved SSEL 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved Watchpoint Message Control 1.
Page 904: Table 471. Gtmdi_Speb_Wpc2 Field Descriptions
GTM Development Interface (GTMDI) RM0400 watchpoint trace messages and to control logic outside the GTMDI module, such as SPU interface. Register index: 36 WTSEL1 STSEL1 TEN1 SEN1 RESET: WTSEL2 STSEL2 TEN2 SEN2 RESET: Figure 418. SPEB watchpoint control 2 register (GTMDI_SPEB_WPC2) Table 471 describes the GTMDI_SPEB_WPC2 register functions.
Page 905 RM0400 GTM Development Interface (GTMDI) Table 471. GTMDI_SPEB_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Output Selection 2. The WTSEL2[2:0] field selects among 8 available watchpoint triggers which one is connected to the DIR SPEB signal. Other modules can selected the same WTSEL2 value, in this case the result signal is an OR of all selected sources. 000 SHARED_WPT[0] 001 SHARED_WPT[1] 14–12...
Page 906: Table 472. Gtmdi_Dpll_Wpc1 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 41 TSEL1 TSS1 HEN1 RESET: TSEL2B TSEL2A HEN2 RESET: Figure 419. DPLL watchpoint control 1 register (GTMDI_DPLL_WPC1) Table 472 describes the GTMDI_DPLL_WPC1 register functions. Table 472. GTMDI_DPLL_WPC1 field descriptions Field Description Watchpoint Selection 1. The TSEL1[1:0] field selects if a watchpoint trigger is issued based on TASI or SASI events.
Page 907: Figure 420. Dpll Watchpoint Control 2 Register (Gtmdi_Dpll_Wpc2)
RM0400 GTM Development Interface (GTMDI) Table 472. GTMDI_DPLL_WPC1 field descriptions(Continued) Field Description Watchpoint Selection 2A. The TSEL2A field selects if a watchpoint is issued based on the RAM1a, RAM1bc or RAM2 access. 9–8 00 Watchpoint is issued based on RAM1a access TSEL2A 01 Watchpoint is issued based on RAM1b access 10 Watchpoint is issued based on RAM2 access...
Page 908: Table 473. Gtmdi_Dpll_Wpc2 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 473. GTMDI_DPLL_WPC2 field descriptions Field Description Watchpoint Trigger Output Selection 1. The WTSEL1[2:0] field selects among 8 available watchpoint triggers which one is connected to the DPLL SASI or TASI signal. Other modules can select this same WTSEL1 value, in this case the result trigger signal is an OR of all selected sources.
Page 909: Table 474. Gtmdi_Dpll_Wpc3 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 473. GTMDI_DPLL_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Enable 2. The TEN2 field controls if a watchpoint external trigger is issued by the DPLL RAM selected access. TEN2 0 Disable External Watchpoint Trigger Generation 1 Enable External Watchpoint Trigger Generation Start/Stop Enable 2.
Page 910: Table 475. Gtmdi_Dpll_Wpc4 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 44 RESET: RAM_ADDR_MASK RESET: Figure 422. DPLL watchpoint control 4 register (GTMDI_DPLL_WPC4) Table 475 describes the GTMDI_DPLL_WPC4 register functions. Table 475. GTMDI_DPLL_WPC4 field descriptions Field Description RAM Address mask. The RAM_ADDR_MASK[11:0] field is a mask applied bit by bit to 11–0 the RAM_ADDR defined in the GTMDI_DPLL_WPC5 register.
Page 911: Table 476. Gtmdi_Dpll_Wpc5 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 476. GTMDI_DPLL_WPC5 field descriptions Field Description RAM Address Compare. The RAM_ADDR[11:0] field defines the address value that is compared against the address for write and read DPLL RAM accesses. Before the comparison is executed the RAM_ADDR_MASK should be considered thus masking 11–0 corresponding bits.
Page 912: Figure 425. Aru Watchpoint Control 1 Register (Gtmdi_Aru_Wpc1)
GTM Development Interface (GTMDI) RM0400 Table 477. GTMDI_DPLL_DTC field descriptions(Continued) Field Description Data Trace Message Control. This bit is written by JTAG interface but can also be controlled at SoC level with dedicated Start/Stop signals inputs to GTMDI. 0 Data Trace Messages disabled 1 Data Trace Messages enabled Start/Stop input signal selection 1.
Page 913: Table 478. Gtmdi_Aru_Wpc1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 478. GTMDI_ARU_WPC1 field descriptions Field Description ARU Debugging Channel 0 Data Activity Selection 1. The TSS1 bit selects the type of data activity to monitor on ARU Debugging Channel 0. 0 Any Data (do not compare data). Watchpoint generation is based on a valid data indication on TSS1 ARU Debugging Channel 0 1 Compare data with expected value...
Page 914: Table 479. Gtmdi_Aru_Wpc2 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 51 WTSEL1 STSEL1 TEN1 SEN1 RESET: WTSEL2 STSEL2 TEN2 SEN2 RESET: Figure 426. ARU watchpoint control 2 register (GTMDI_ARU_WPC2) Table 479 describes the GTMDI_ARU_WPC2 register functions. Table 479. GTMDI_ARU_WPC2 field descriptions Field Description Watchpoint Trigger Output Selection 1.
Page 915: Figure 427. Aru Watchpoint Data0H Register (Gtmdi_Aru_Data0H)
RM0400 GTM Development Interface (GTMDI) Table 479. GTMDI_ARU_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Output Selection 2. The WTSEL2[2:0] field selects among 8 available watchpoint triggers which one is connected to the ARU Debugging Channel 1. Other modules can selected the same WTSEL2 value, in this case the result signal is an OR of all selected sources. 000 SHARED_WPT[0] 001 SHARED_WPT[1] 14–12...
Page 916: Table 480. Gtmdi_Aru_Data0H Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 480. GTMDI_ARU_DATA0H field descriptions Field Description 28–0 Watchpoint DATA0H. This field is compared against the high word of the ARU Debugging Channel 0. DATA0H 42.5.1.23 ARU watchpoint DATA0L register (GTMDI_ARU_DATA0L) The ARU Watchpoint DATA0H low word shown in Figure 428 is used for comparison against the low word of the ARU Debugging Channel 0.
Page 917: Table 482. Gtmdi_Aru_Data1H Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 482 describes the GTMDI_ARU_DATA1H register functions. Table 482. GTMDI_ARU_DATA1H field descriptions Field Description 28–0 Watchpoint DATA1H. This field is compared against the high word of the ARU Debugging Channel 1. DATA1H 42.5.1.25 ARU watchpoint DATA1L register (GTMDI_ARU_DATA1L) The ARU Watchpoint DATA1L low word shown in Figure 430 is used to be compared...
Page 918: Table 484. Gtmdi_Aru_Dtc Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: 56 STSEL1 DMC1 SEN1 RESET: STSEL2 DMC2 SEN2 RESET: Figure 431. ARU data trace control register (GTMDI_ARU_DTC) Table 484 describes the GTMDI_ARU_DTC register functions. Table 484. GTMDI_ARU_DTC field descriptions Field Description Start/Stop input signal selection 1. Selects the Start/Stop input that is used by the ARU Debugging Channel 0 data trace messages.
Page 919 RM0400 GTM Development Interface (GTMDI) Table 484. GTMDI_ARU_DTC field descriptions(Continued) Field Description Data Trace Message Control. This bit controls ARU data trace message transmission for ARU Debugging Channel 1. This bit is written by the JTAG interface but can also be controlled at SoC level by dedicated Start/Stop signals, inputs to GTMDI.
Page 920: Table 485. Gtmdi_Mcsa_Dc And Gtmdi_Mcsb_Dc Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 485. GTMDI_MCSA_DC and GTMDI_MCSB_DC field descriptions Field Description MCSA/B Selection field. The MCSA/B_SEL[3:0] selection field selects which one of the MCS cores in the GTM module are assigned as MCSA/B. 0000 MCS0 0001 MCS1 0010 Reserved 0011 Reserved 0100 Reserved...
Page 921: Table 486. Gtmdi_Mcsa_Wpc And Gtmdi_Mcsb_Wpc Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 486. GTMDI_MCSA_WPC and GTMDI_MCSB_WPC field descriptions Field Description Halt/Watchpoint on Active Channel. The HACH field selects which type of MCS RAM access generates a watchpoint or halt. Combining this field with HWO gives GTMDI the capability of monitoring channel activity as well as accesses to specific addresses or data.
Page 922 GTM Development Interface (GTMDI) RM0400 Table 486. GTMDI_MCSA_WPC and GTMDI_MCSB_WPC field descriptions(Continued) Field Description Watchpoint Trigger Enable.The TEN field controls if a external trigger is issued by the MCSA/B when a watchpoint occurs. 0 Disables Trigger Generation 1 Enables Trigger Generation Start/Stop Enable.
Page 923: Table 487. Gtmdi_Mcsa_Ptc And Gtmdi_Mcsb_Ptc Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 487. GTMDI_MCSA_PTC and GTMDI_MCSB_PTC field descriptions Field Description Program Fetch Trace Start. This bit field allows Program fetch trace to be enabled at a watchpoint occurrence. See Figure 436, Figure 437, Figure 438 Figure 439 for definition about watchpoint 1 and 2.
Page 924: Table 488. Gtmdi_Mcsa_Dtc And Gtmdi_Mcsb_Dtc Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 488. GTMDI_MCSA_DTC and GTMDI_MCSB_DTC field descriptions Field Description Range Control 0. Controls the range on data trace window 0. The window 0 is defined by DTAR1 register. See Figure 441. 0 Trace addresses outside (exclusive) of data trace window 0 1 Trace address inside (inclusive) of data trace window 0 Range Control 1.
Page 925: Table 489. Gtmdi_Mcsa_Wpa1 And Gtmdi_Mcsb_Wpa1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) 42.5.1.31 MCSA/B watchpoint address 1 register (GTMDI_MCSA_WPA1 and GTMDI_MCSB_WPA1) The MCSA/B Watchpoint Address Registers 1 shown in Figure 436 are used to configure the MCSA/B halt/watchpoint hardware. They are used for data and instruction fetch accesses.
Page 926: Table 490. Gtmdi_Mcsa_Wpa2 And Gtmdi_Mcsb_Wpa2 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: MCSA–66 / MCSB–83 HWAM RESET: RESET: Figure 437. MCSA/B watchpoint address 2 register (GTMDI_MCSA_WPA2 and GTMDI_MCSB_WPA2) Table 490 describes the GTMDI_MCSA_WPA2 and GTMDI_MCSB_WPA2 register functions. Table 490. GTMDI_MCSA_WPA2 and GTMDI_MCSB_WPA2 field descriptions Field Description Halt/Watchpoint Address Mask.
Page 927: Table 491. Gtmdi_Mcsa_Wpd1 And Gtmdi_Mcsb_Wpd1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 491. GTMDI_MCSA_WPD1 and GTMDI_MCSB_WPD1 field descriptions Field Description Halt/Watchpoint Data. The HWD field is used to compare data operands in a RAM read or write access. Depending upon the size of the access, only certain bits of HWD are compared against the the RAM data.
Page 928: Table 493. Gtmdi_Mcsa_Ce And Gtmdi_Mcsb_Ce Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: MCSA–69 / MCSB–86 CFTE CDTE RESET: WPCE RESET: Figure 440. MCSA/B channel enable register (GTMDI_MCSA_CE and GTMDI_MCSB_CE) Table 493 describes the GTMDI_MCSA_CE and GTMDI_MCSB_CE register functions. Table 493. GTMDI_MCSA_CE and GTMDI_MCSB_CE field descriptions Field Description MCSA/B Channel Fetch Trace Enable.
Page 929 RM0400 GTM Development Interface (GTMDI) Table 493. GTMDI_MCSA_CE and GTMDI_MCSB_CE field descriptions(Continued) Field Description MCSA/B Channel Data Trace Enable. The CDTE[7:0] is an one hot bit field which defines the channel or channels to be monitored for data trace messages. If enabled, the corresponding channel Data Accesses are monitored by Data Trace messages.
Page 930: Table 494. Gtmdi_Mcsa_Dtar1 And Gtmdi_Mcsb_Dtar1 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Register index: MCSA–71 / MCSB–88 DTSA [13:2] RESET: DTEA [13:2] RESET: Figure 441. Data trace address range 1 register (GTMDI_MCSA_DTAR1 and GTMDI_MCSB_DTAR1) Note: The DTSA and DTEA fields represent word addresses relative to the MCS address map, not the CPU address.
Page 931: Table 495. Gtmdi_Mcsa_Dtar2 And Gtmdi_Mcsb_Dtar2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 495 describes the GTMDI_MCSA_DTAR2 and GTMDI_MCSB_DTAR12 register functions. Table 495. GTMDI_MCSA_DTAR2 and GTMDI_MCSB_DTAR2 field descriptions Field Description 29–18 Data Trace Start Address. The DTSA field is the start address for MCSA/B data trace window. DTSA 13–2 Data Trace End Address.
Page 932: Table 496. Gtmdi_Tbu0_Wpc1 Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 496. GTMDI_TBU0_WPC1 field descriptions Field Description TBU0 Watchpoint 1 Compare Selection. The TSS1[2:0] field controls the type of comparison used for TBU0 watchpoint generation. 000 TBU0 24-bit update (do not compare data) 001 TBU 27-bit update (do not compare data) 30–28 010 Compare TBU0 value in 24-bit mode with expected data TSS1...
Page 933: Table 497. Gtmdi_Tbu0_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) 42.5.1.39 TBU0 watchpoint control 2 register (GTMDI_TBU0_WPC2) The GTMDI_TBU0_WPC2 shown in Figure 444 register controls the Watchpoint Triggers issued by TBU0. These triggers are used for GTM to enter Halt state, generate watchpoint messages and control logic external to GTMDI, such as in the SPU interface. Register index: 95 WTSEL1 STSEL1...
Page 934: Figure 445. Tbu0 Watchpoint Data Register (Gtmdi_Tbu0_Data)
GTM Development Interface (GTMDI) RM0400 Table 497. GTMDI_TBU0_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Output Selection 2. The WTSEL2[2:0] field selects among 8 available watchpoint triggers which one is connected to the TBU0 selected event. Other modules can selected the same WTSEL2 value, in this case the result signal is an OR of all selected sources. 000 SHARED_WPT[0] 001 SHARED_WPT[1] 14–12...
Page 935: Table 498. Gtmdi_Tbu0_Data Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 498. GTMDI_TBU0_DATA field descriptions Field Description 26–0 TBU0 Watchpoint DATA. The field TBU0_DATA is used to compare against the TBU0 data. TBU0_DATA 42.5.1.41 TBU1 watchpoint control 1 register (GTMDI_TBU1_WPC1) The GTMDI_TBU1_WPC1 register shown in Figure 446 controls the Watchpoint issued by TBU1 GTM Time Base Units.
Page 936: Figure 447. Tbu1 Watchpoint Control 2 Register (Gtmdi_Tbu1_Wpc2)
GTM Development Interface (GTMDI) RM0400 Table 499. GTMDI_TBU1_WPC1 field descriptions(Continued) Field Description Watchpoint Message Control 1. The WMC1 Watchpoint Message Control 1 bit controls the watchpoint message sent through the Message Data bus. If this bit is set it enables valid matches or increment on selected TBU1 to generate a watchpoint message.
Page 937: Table 500. Gtmdi_Tbu1_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 500. GTMDI_TBU1_WPC2 field descriptions Field Description Watchpoint Trigger Selection 1. The WTSEL1[2:0] field selects among 8 available watchpoint triggers which one is connected to the TBU1 selected event, match or increment. Other modules can selected the same WTSEL1 value, in this case the result selection is an OR of all selected sources.
Page 938: Table 501. Gtmdi_Tbu1_Data Field Descriptions
GTM Development Interface (GTMDI) RM0400 Table 500. GTMDI_TBU1_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Enable 2. The TEN1 field controls if a watchpoint external trigger is issued by the TBU1 selected event. TEN2 0 Disable Trigger Generation 1 Enable Trigger Generation Start/Stop Enable 2.
Page 939: Table 502. Gtmdi_Tbu2_Wpc1 Field Descriptions
RM0400 GTM Development Interface (GTMDI) control bits from the GTMDI_TBU2_WPC2 register need to be set in order to allow external Start/Stop signals to control the WMC1/2 bits. Register index: 108 TSS1 HEN1 WMC1 RESET: TSS2 HEN2 WMC2 RESET: Figure 449. TBU2 watchpoint control 1 register (GTMDI_TBU2_WPC1) Table 502 describes the GTMDI_TBU2_WPC1 register functions.
Page 940: Figure 450. Tbu2 Watchpoint Control 2 Register (Gtmdi_Tbu2_Wpc2)
GTM Development Interface (GTMDI) RM0400 Table 502. GTMDI_TBU2_WPC1 field descriptions(Continued) Field Description Halt Enable 2. The HEN2 Halt Enable 2 bit controls if the TBU2 valid event, which is a match or increment, is enabled to HALT the GTM module. If this bit is set and an event occurs on the TBU2, a Halt signal is generated to the GTM which enters Halt state.
Page 941: Table 503. Gtmdi_Tbu2_Wpc2 Field Descriptions
RM0400 GTM Development Interface (GTMDI) Table 503. GTMDI_TBU2_WPC2 field descriptions Field Description Watchpoint Trigger Selection 1. The WTSEL1[2:0] field selects among 8 available watchpoint triggers which one is connected to the TBU2 selected event, match or increment. Other modules can selected the same WTSEL1 value, in this case the result selection is an OR of all selected sources.
Page 942: Unimplemented Registers
GTM Development Interface (GTMDI) RM0400 Table 503. GTMDI_TBU2_WPC2 field descriptions(Continued) Field Description Watchpoint Trigger Enable 2. The TEN1 field controls if a watchpoint external trigger is issued by the TBU2 selected event. TEN2 0 Disable Trigger Generation 1 Enable Trigger Generation Start/Stop Enable 2.
Page 943: Debug Enable Logic
RM0400 GTM Development Interface (GTMDI) 42.6.1 Debug enable logic In order to enable the GTM to enter Halt state, which is the module debug state, there are some registers that need to be set. The sources that can put GTM in halt state are events from TIM, TOM, ATOM, MCS and several other internal GTM modules that are selected and controlled by the GTMDI_DC register bits shown in Figure...
Page 944: Gtmdi Reset Configuration
GTM Development Interface (GTMDI) RM0400 Figure 453. TIM selection logic STSEL1 SEN1 Watchpoint logic 1 External start/stop start/stop sel message control (SPU) WMC1 Inputs from others Watchpoint message GTM sub-modules Filter out CHSEL1 SSEL1 HEN1 TSS1 slope GTM HALT Message TIM1 queue WTSEL1...
Page 945: Message Data Bus —Interface With Nar Module
RM0400 GTM Development Interface (GTMDI) 42.6.3.2 Enabling GTMDI class 3 operation After exiting JTAG TEST-LOGIC-RESET state, the GTMDI classes 1 and 3 are enabled, otherwise the GTMDI class 3 features are disabled, entering in the Disable-Port Mode, thus no trace output is provided, and auxiliary port output pins are disabled. 42.6.4 Message Data Bus —interface with NAR module 42.6.4.1...
Page 946 GTM Development Interface (GTMDI) RM0400 Table 505. GTMDI Nexus trace message formats(Continued) Message Packet Packet packet packet Packet description name type name size (bits) size (bits) fixed TCODE Value = 15 fixed GTMDI source ID. Value = 0x7 Watchpoint Number indicating watchpoint source (binary coded), fixed WPHIT Message...
Page 947: Table 506. Debug Status Field Format
RM0400 GTM Development Interface (GTMDI) Table 505. GTMDI Nexus trace message formats(Continued) Message Packet Packet packet packet Packet description name type name size (bits) size (bits) fixed TCODE Value = 61 fixed GTMDI source ID. Value = 0x7 DPLL Data fixed DATA Data value read/written...
Page 948: Table 509. Watchpoint Field Wphit[11:0] Format For Wphit[14:12] = 0B001
GTM Development Interface (GTMDI) RM0400 Table 508. Watchpoint field WPHIT[11:0] format for WPHIT[14:12]= 0b000(Continued) WPHIT bit Selected source ATOM 0 Negedge ATOM 0 Posedge TOM 1 Negedge TOM 1 Posedge TOM 0 Negedge TOM 0 Posedge TIM 1 Negedge TIM 1 Posedge TIM 0 Negedge TIM 0 Posedge Table 509.
Page 949: Ieee 1149.1 (Jtag) Input Port
RM0400 GTM Development Interface (GTMDI) Table 510. Watchpoint field WPHIT[11:0] format for WPHIT[14:12] = 0b010(Continued) WPHIT bit Selected source SPEB (NIPD NEGEDGE) SPEB (NIPD POSEDGE) 11:8 Reserved Table 511. Watchpoint field WPHIT[11:0] format for WPHIT[14:12] = 0b011 WPHIT - bit Selected source TBU0 Watchpoint 1 TBU0 Watchpoint 2...
Page 950: Table 512. Implemented Instructions
GTM Development Interface (GTMDI) RM0400 Table 512. Implemented instructions Private Instruction name Opcode Description public NEXUS-ENABLE Public 4b0000 Activate Nexus controller state machine to read and write GTMDI registers Implements a single shift register stage providing a minimum serial length BYPASS Public 4b1111...
Page 951: Figure 455. Ieee 1149.1 16-State Finite State Machine
RM0400 GTM Development Interface (GTMDI) Figure 455. IEEE 1149.1 16-State finite state machine TEST LOGIC RESET SELECT-DR-SCAN RUN-TEST/IDLE SELECT-IR-SCAN CAPTURE-DR CAPTURE-IR SHIFT-IR SHIFT-DR EXIT1-DR EXIT1-IR PAUSE-DR PAUSE-IR EXIT2-IR EXIT2-DR UPDATE-DR UPDATE-IR NOTE: The value shown adjacent to each state transition in this figure represents the value of the TMS bit at the time of a rising edge of TCK.
Page 952: Table 513. Loading Nexus-Enable Instruction
GTM Development Interface (GTMDI) RM0400 42.6.5.2 Loading NEXUS-ENABLE instruction Access to the GTMDI registers is enabled when the TAP controller instruction register is loaded with the NEXUS-ENABLE instruction. The current instruction value is loaded into the IEEE 1149.1 shifter in the CAPTURE-IR state. The instruction is shifted in via the SELECT- IR-SCAN path and loaded in the UPDATE-IR state.
Page 953: Table 514. Writing To A Register
RM0400 GTM Development Interface (GTMDI) All register access is performed via the SELECT-DR-SCAN path. The Nexus state machine defaults to the register select state when enabled. Accessing a register requires two passes through the SELECT-DR-SCAN path: one pass to select the register and the second pass to read/write the register.
Page 954: Nexus Class 1 Development Support
GTM Development Interface (GTMDI) RM0400 42.6.6 Nexus Class 1 development support The GTMDI contains a number of hardware hooks that aid in the development of software for the GTM MCS cores. This features described in this section are compliant with the following Nexus Class 1 features: •...
Page 955: Figure 460. Data Write Message Format
RM0400 GTM Development Interface (GTMDI) 42.6.8.1 MCS data write message The MCS data write message contains the data write value and the address of the RAM target location. The data write message format is shown in Figure 460. Figure 460. Data write message format 6 bits K bits 1 bit...
Page 956: Figure 462. Gtmdi Generic Data Trace Flow Diagram
GTM Development Interface (GTMDI) RM0400 Figure 462. GTMDI generic data trace flow diagram Reset Data Trace Enabled Data Read/Write Detected Generate Queue Error Event Address in any DTAR Queue Event Store Data Trace Snapshot Queue Full? 42.6.8.3.1 MCS data trace windowing Data trace windowing is provided so that the development tool can decrease the auxiliary port usage by limiting the accesses that are traced.
Page 957: Fetch Trace
RM0400 GTM Development Interface (GTMDI) Figure 463. Data trace address range options Programmed Value Range Selected DTSA =< DTEA [DTSA: DTEA] DTSA > DTEA All addresses are out of range 1. Since all addresses are considered to be out of range, a Data Trace Event may be recognized if the DTC register is programmed so that addresses out of range are queued.
Page 958: Figure 464. Fetch Trace State Machine State Diagram
GTM Development Interface (GTMDI) RM0400 may be changed in the middle of a program execution, program fetch trace may be enabled or disabled during program execution as well. 42.6.9.2 Fetch trace state machine The fetch trace state machine is composed basically by three states: start, running and end. When the fetch trace is enabled, fetch state machine goes to the start state.
Page 959: Watchpoint Trace
RM0400 GTM Development Interface (GTMDI) At the moment the previous message is generated, the corresponding MCS fetch trace buffer may or may not be full. If the buffer is not full, the message is inserted into the buffer and the fetch trace state machine continues in the running state, otherwise a fetch trace error message is generated for the corresponding MCS and the fetch trace state machine goes to the start state.
Page 960 GTM Development Interface (GTMDI) RM0400 Enable the Nexus TAP controller Retrieve Device ID if needed Load the Nexus TAP controller with the NEXUS-ENABLE instruction To write control data to GTMDI tool-mapped registers, the following sequence is required: Write the 7-bit register index and set the write bit to select register with a pass through the SELECT-DR-SCAN path in the JTAG state machine Write the register value with a pass through the SELECT-DR-SCAN path.
Page 961: Introduction
RM0400 GTM101 Integration (GTMINT) Module GTM101 Integration (GTMINT) Module 43.1 Introduction This chapter specifies the functionality of the GTMINT module. The GTMINT is integrated IP with timer and debug functions and is composed of: • The Bosch GTM-IP_101 timer module (also called GTM-IP) •...
Page 962 GTM101 Integration (GTMINT) Module RM0400 – IEEE 1149.1 (JTAG) Test Access Port (TAP) Support for optional Multi-JTAG TAP Linking Module (TLM) 4 pins (TDI, TDO, TMS, and TCK) Reset input TRST driven by either the Nexus Port Controller or an external –...
Page 963: Modes Of Operation
RM0400 GTM101 Integration (GTMINT) Module – Correctable error indication (correctable data error) • Generation of 103 interrupt requests and or DMA requests. • Debugger is allowed to read all GTM registers through the peripheral bus even when the timer is running. Read-access of the debugger is possible without destroying or changing the contents of these registers.
Page 964: Memory Map And Register Definition
GTM101 Integration (GTMINT) Module RM0400 Figure 466. GTMINT block diagram To/From IRQ/ From/To INTC & DMAC Interface GTM-IP Clocks To/From RAMs signals MEMU GTMDI Clocks Debug Interface 43.2 Memory map and register definition This section provides a reference table to the GTM-IP submodule registers. Details of each register are found in the GTM-IP specification document.
Page 965 RM0400 GTM101 Integration (GTMINT) Module Table 515. High level memory map(Continued) Offset 0x00000300 0x00000600 0x00000800 SPE0 0x00000880 SPE1 0x00000F00 0x00000F40 MCFG 0x00001000 TIM0 0x00001800 TIM1 0x00008000 TOM0 0x00008800 TOM1 0x0000D000 ATOM0 0x0000D800 ATOM1 0x0000E000 ATOM2 0x00018000 F2A0 0x00018080 AFD0 0x00018400 FIFO0 0x00019000 FIFO0_MEMORY...
Page 966: Table 516. Gtmint Module Memory Map
GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map Offset Access Reset value Location GTM-IP TOP-Level Configuration Registers 0x101X_XXXX See GTM 0x00000 GTM-IP Version control register (GTM_REV) Spec. 0x00004 GTM-IP Global reset register (GTM_RST) 0x0000_0000 See GTM Spec. 0x00008 GTM-IP Global control register (GTM_CTRL) 0x0000_0001...
Page 967 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location TBU channel m control (m = 0..2) 0x00104+m*0x08 0x0000_0000 See GTM Spec. (TBU_CH[m]_CTRL) TBU channel n base (n = 0...2) 0x00108+n*0x08 0x0000_0000 See GTM Spec. (TBU_CH[n]_BASE) 0x0011C –...
Page 968 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location Debug access channel 1 0x00298 0x0000_01FE See GTM Spec. (ARU_DBG_ACCESS1) Debug access 1 transfer register upper data 0x0029C 0x0000_0000 See GTM Spec. word (ARU_DBG_DATA1_H) Debug access 1 transfer register lower data 0x002A0 0x0000_0000...
Page 969 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location ICM Interrupt group register covering DPLL 0x00604 0x0000_0000 See GTM Spec. (ICM_IRQG_1) ICM Interrupt group register covering TIM0, 0x00608 0x0000_0000 See GTM Spec. TIM1, TIM2 (ICM_IRQG_2) 0x0060C Reserved ICM Interrupt group register covering MCS0...
Page 970 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location SPE Interrupt notification register 0x0082C + AAi 0x0000_0000 See GTM Spec. (SPE[i]_IRQ_NOTIFY) SPE Interrupt enable register 0x00830 + AAi 0x0000_0000 See GTM Spec. (SPE[i]_IRQ_EN) SPE Interrupt generation by software 0x00834 + AAi 0x0000_0000...
Page 971 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location 0x01018+n*0x80 + Channel n TDU control (TIM[i]_CH[n]_TDUV) 0x0000_0000 See GTM Spec. 0x0101C+n*0x80 + Channel n filter parameter 0 0x0000_0000 See GTM Spec. (TIM[i]_CH[n]_FLT_RE) 0x01020+n*0x80 + Channel n filter parameter 1 0x0000_0000 See GTM Spec.
Page 972 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location 0x0800C + n*0x0040 TOM Channel n CCU0 compare register 0x0000_0000 See GTM Spec. + CCi (TOM[i]_CH[n]_CM0) 0x08010 + n*0x0040 TOM Channel n CCU1 compare register 0x0000_0000 See GTM Spec.
Page 973 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location TGC1 enable/disable control reg 0x08270 + CCi 0x0000_0000 See GTM Spec. (TOM[i]_TGC1_ENDIS_CTRL) TGC1 enable/disable status reg 0x08274 + CCi 0x0000_0000 See GTM Spec. (TOM[i]_TGC1_ENDIS_STAT) TGC1 output enable control reg 0x08278 + CCi 0x0000_0000...
Page 974 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location (0x0D030 – 0x0D03C) + Reserved for ATOM[i]_CH[m] m*0x0080 + DDi AGC Global control register 0x0D040 + DDi 0x0000_0000 See GTM Spec. (ATOM[i]_AGC_GLB_CTRL) AGC0 Enable/disable control register 0x0D044 + DDi 0x0000_0000 See GTM Spec.
Page 975 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location 0x18084+m*0x10 – Reserved for AFD 0x1808C+m*0x10 0x18100 – 0x183FC Reserved FIFO Configuration Registers (m = 0...7, i = 0) FIFO Channel m control register 0x18400+m*0x40 0x0000_0000 See GTM Spec.
Page 976 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location 0x1C000 – Reserved for F2A1, AFD1, FIFO1, and FIFO1 MEM 0x1DFFC 0x1E000 – 0x27FFC Reserved Digital PLL Module (DPLL) 0x28000 Control Register 0 (DPLL_CTRL_0 0x003B_BA57 See GTM Spec.
Page 977 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location Interrupt force register 0x28048 0x0000_0000 See GTM Spec. (DPLL_IRQ_FORCINT) 0x2804C Interrupt mode register (DPLL_IRQ_MODE) 0x0000_0000 See GTM Spec. Error Interrupt enable register 0x28050 0x0000_0000 See GTM Spec.
Page 978 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location RAM Region 1a (0.288 KB for 96 words of 24 bits) ACTION_n Position/Value action request 0x28200 + n*0x0004 0x0000_0000 See GTM Spec. Register (PSAn), n = 0...23 0x28260 + ACTION_m time to react before PSAm 0x0000_0000...
Page 979 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location Time out value of active STATE slope 0x28434 0x0000_0000 See GTM Spec. (TOV_S) Calculated ADD_IN value for normal 0x28438 0x0000_0000 See GTM Spec. SUB_INC1 generation (ADD_IN_CAL1) Calculated ADD_IN value for normal 0x2843C 0x0000_0000...
Page 980 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location absolute error of prediction for last STATE 0x28488 0x0000_0000 See GTM Spec. increment (EDT_S) Average absolute error of prediction up to the 0x2848C 0x0000_0000 See GTM Spec.
Page 981 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location Measured position stamp of last but one 0x285F4/ 0x285F0 0x0000_0000 See GTM Spec. STATE input (PSSM_old) Number of pulses of current increment in 0x285F8 0x0000_0000 See GTM Spec.
Page 982 GTM101 Integration (GTMINT) Module RM0400 Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location control bits for actions 20...23 0x28F14 0x0000_0000 See GTM Spec. (DPLL_ACB_5) control bits for actions 24...27 0x28F18 0x0000_0000 See GTM Spec. (DPLL_ACB_6) control bits for actions 28...31 0x28F1C 0x0000_0000 See GTM Spec.
Page 983 RM0400 GTM101 Integration (GTMINT) Module Table 516. GTMINT module memory map(Continued) Offset Access Reset value Location MCS Set trigger control register 0x3002C + FFi 0x0000_0000 See GTM Spec. (MCS[i]_STRG) (0x30028 – 0x3002C) + n*0x80 Reserved (n > 0) + FFi (0x30030 –...
Page 984: Register Descriptions
GTM101 Integration (GTMINT) Module RM0400 2. For detailed information see the GTM-IP Specification document. 3. Reset value depends on configuration parameters. 4. RAM reserved position for GTM-IP internal use. No error occurs when accessed. 43.2.2 Register descriptions This section contains the description of additional registers on the top integration module. Description of GTM-IP registers, or GTMDI registers are found in their respective specification document.
Page 985: Table 518. Gtmintclr Field Descriptions
RM0400 GTM101 Integration (GTMINT) Module Table 517. GTMMCR field descriptions(Continued) Field Description AEISREN AEI interface soft-reset control enable. The AEISREN bit enables the soft-reset of the AEI interface that is controlled by AEISRST bit in the GTMMAEICR. Please refer to Section 43.3.7, AEI Interface Software Reset Description for more details.
Page 986 GTM101 Integration (GTMINT) Module RM0400 Table 519. Correspondence between the INTCLR_PTR and the interrupts outputs(Continued) INTCLR_PTR[0:9] Interrupt output signal to be cleared 0x2C6 Reserved 0x2C7 ipi_int_gtm_cmp 0x2C8 ipi_int_gtm_spe0 0x2C9 ipi_int_gtm_spe1 0x2CA to 0x2D1 714 to 721 ipi_int_gtm_psm0[0]–[7] 0x2D2 to 0x2EC 722 to 748 ipi_int_gtm_dpll[0]–[26] 0x2ED to 0x2F4...
Page 987: Functional Description
RM0400 GTM101 Integration (GTMINT) Module Offset 0x000CC Access: User read/write Reset Reset Figure 469. GTM AEI Control Register (GTMMAEICR) GTMMAEICR register functions are as shown in Table 520. Table 520. GTMMAEICR field descriptions Field Description AEISRST AEI interface soft-reset control. The AEISRST bit when set applies a reset on the GTM-IP AEI interface.
Page 988: Table 521. Submodules Of Gtm-Ip
GTM101 Integration (GTMINT) Module RM0400 generic. The scalability and configurability is reached with an architecture philosophy where dedicated hardware submodules are located around a central routing unit called Advanced Routing Unit (ARU). The ARU can connect the submodules in a flexible manner. The connectivity is software programmable and can be configured during runtime.
Page 989: Gtmdi Debug Interface
RM0400 GTM101 Integration (GTMINT) Module Table 521. Submodules of GTM-IP(Continued) Submodule Group Memory Configuration Module (MCFG) Infrastructural component for MCS TIM0 Input Mapping Module (MAP) Dedicated Digital PLL (DPLL) Sensor Pattern Evaluation Module (SPE) BLDC support Interrupt Concentrator Module (ICM) Interrupt services Output Compare Unit (CMP) Safety features...
Page 990: Table 522. Ecc Characteristics For Gtm Memories
GTM101 Integration (GTMINT) Module RM0400 Memories of this block are equipped with error detection features for safety improvement. The following procedures detect errors on memory accesses: • Memory write data and its address are considered in the parity bits calculation. These parity bits are stored in that memory address as part of the written data.
Page 991: Table 523. 42 Bits Word Based Syndrome Definition
RM0400 GTM101 Integration (GTMINT) Module Table 523. 42 bits Word Based Syndrome Definition SYND[6:0] / SYND[6:0] / Error result Matrix element Error result Matrix element Element value Element value (for SMATRIX) (for MATRIX) (for SMATRIX) (for MATRIX) (hex) (hex) error on code bit 6 —...
Page 992: Stop Mode Description
GTM101 Integration (GTMINT) Module RM0400 43.3.3.2 Error Report Description Each RAM generates a defined number of information to report an error on an access. Each of them is described below. • Error Address – this is the mapped address of the RAM as defined in Section 43.2.1, Module memory map.
Page 993: Debug / Halt Mode Description
RM0400 GTM101 Integration (GTMINT) Module 43.3.5 Debug / Halt Mode Description The debug / halt mode is requested via GTMDI and is used to debug the GTM-IP sub-block. In this mode it is required that the core of GTM-IP becomes halted by stopping its clock. Therefore all time bases and counters are frozen.
Page 994: Initialization/Application Information
GTM101 Integration (GTMINT) Module RM0400 It is required to maintain the configuration register IRQ_MODE = 00 that is the Level Interrupt Mode, the default mode to be compatible with the chip standard. the IRQ_NOTIFY register is the internal flag and can be enabled to set an external signal by the IRQ_EN register.
Page 995 RM0400 GTM101 Integration (GTMINT) Module logic, and registers inside the GTM-IP block. Just after this reset signal is negated, the GTM-IP is in the following condition: • The GTM bridge is in asynchronous mode. • after reset, write operations waits the response status (write response is not masked). •...
Page 996: Introduction
CAN Subsystem RM0400 CAN Subsystem 44.1 Introduction The Controller Area Network (CAN) subsystem consists of the modular CAN (M_CAN) modules with an integrated intelligent CAN RAM controller. The CAN RAM controller consists of additional logic for arbitration between the requests for the RAM access by the various CANs and CPU, ECC encoder/decoder for the Message RAM data and active transmit message buffer protection from CPU write access.
Page 997: Features
RM0400 CAN Subsystem Figure 470. CAN subsystem generic block diagram PBRIDGE 0 Clock PBRIDGE 0 CAN Clock CAN protocol CAN bus interface M_CAN RX/TX clock and module clock Host Clock Peripheral Bridge RAM/ECC Controller Common Shared access CAN Clock M_CANx Single-point RX/TX arbiter...
Page 998: Modular Can Cores
CAN Subsystem RM0400 44.3 Modular CAN cores CAN functionality conforms to CAN specification V2.0B active for each CAN node.The M_CAN performs communication according to the CAN protocol specification 2.0 part A,B and to CAN FD 1.0.Flexible assignment of Message Objects to nodes. The bit rate can be programmed to values up to 1 Mbit/s.
Page 999: Features
RM0400 CAN Subsystem 44.3.1 Features The following are the features of Modular CAN cores. • Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1 • CAN Flexible data-rate (CAN–FD ) protocol with maximum 8 data bytes is supported •...
Page 1000: Block Diagram
CAN Subsystem RM0400 44.3.2 Block diagram Figure 471. M_CAN core block diagram Extension Interface M_CAN CAN Tx CAN Core CAN Rx Sync Tx_State Tx_Req 8/16/32 Host IF Tx Handler Tx Prioritization Rx_State Rx Handler Acceptance Filter Memory IF CAN Clock Domain Host Clock Domain •...

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